Intel’s Ivy Bridge Graphics Architecture

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Tesselation

Ivy Bridge incorporates fairly substantial changes to the fixed function hardware in the global domain to support DirectX 11 and enhance performance. One of the new features in DX11 is tesselation and the associated shaders. Hull shaders transform primitives from vertex co-ordinates into tesselation patches and set up the control information. The fixed function tesselation hardware receives input from the hull shader and sub-divides the patch into as many as 64 output patches. The Ivy Bridge tesselator takes advantage of the URB and can emit a domain point every clock. The domain shaders take the output patches and calculate vertex co-ordinates to translate the tesselated output back to the original frame of reference. The geometry, clipping and setup stages, which are fixed functions in the graphics pipeline have also been scaled up to achieve higher throughput, through better scoreboarding and a variety of other techniques.

Display

Display technology has stagnated for a number of years as the industry has struggled to deal with economic limitations and the difficulty in persuading consumers to choose higher quality displays. The vast majority of videos are available in 1080p, and it is rare for monitors to exceed a 2560×1600 resolution. The pixel density for displays has remained relatively constant, at around 100-150 pixels-per-inch.

Conveniently, the iPad 3 has catalyzed the display market. The LCD used by Apple is just over 250 pixels-per-inch, so about twice the density of a conventional display. In part due to Apple’s superb marketing, consumers seem to be much more interested in visual quality. Perhaps most importantly, it demonstrates that some buyers will demand and pay a premium for high density displays.

The classic PC vendors are very cost sensitive and unwilling to take risks and increase prices to introduce higher quality offerings. There are rumors swirling that the next generation of MacBooks and iMacs will feature similar display technology. If these rumors prove true, it would prompt PC and vendors to launch competing high density displays for premium products, simply for competitive reasons. Once the broader industry gets started, the investment will eventually reduce the price to reasonable levels for volume products.

Ivy Bridge was already slated to handle 3 independent displays, compared to 2 for the previous generation. However, the design team made a very late change to the product plan to include high resolution 4K (4096×2304) video and display. While 4K displays are hideously expensive, this will be appreciated by video professionals. Intel’s move guarantees that the industry will have the support that is necessary to begin producing and selling high density displays for PCs. While this is unlikely to make a difference for cost sensitive PCs, it would be critical for early adopters like Apple.

Media and Scheduling

Media has been always been a central focus for Intel’s graphics team, because it is the dominant graphics usage model for corporate PCs. While few travelers care about gaming on a plane ride, watching a movie is second nature.

The media and graphics pipelines in Sandy Bridge and Ivy Bridge share a huge amount of functionality. Both rely on the shader array for computation, and the sampling pipeline is used for both graphics and media workloads. This means that many enhancements in the GPU benefit both graphics and media. Sandy Bridge already featured the best video encoding and decoding hardware in the industry, but Intel is not known for standing still.

The multi-format codec engine is a dedicated hardware block in Intel’s GPUs that is used for the most taxing parts of video processing. Since Intel opted for 4K resolution output, the video processing needs to scale up proportionally. The entropy decoder in Ivy Bridge was redesigned for 4K resolutions and much higher performance, and is used for both video decode and encode.

More importantly, the scheduling for media and graphics workloads is much more flexible. In Sandy Bridge, media encoding was split into two stages. The first was a software encoder that executed programmable media shaders, and the second used the multi-format codec. These two stages operated synchronously and the shader array was available to either media shaders or graphics shaders, but not both.

Ivy Bridge introduces two levels of concurrency for media encoding. The first, is that the programmable media processing and fixed functions stages are now asynchronous. Each stage can concurrently operate on different frames within the same stream. The second level of concurrency is that the media and graphics shaders can now share the shader array in time slices. Previously, the media and graphics pipelines would block one another.


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