Medfield, Intel’s x86 Phone Chip

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Intel’s mobile strategy is a case study that highlights both the strengths and weaknesses of the company. The negatives are all obvious in the rear view mirror; it simply takes a tremendous period of time for Intel to fully align their roadmaps for manufacturing, design and marketing. It doesn’t help that Intel started from a position that was not focused on mobile at all.

Intel’s first “ultramobile” product was Silverthorne, released in 2008 on a high performance 45nm process, and accompanied by a 130nm chipset. The notion of Silverthorne in a smart phone is absolutely laughable. There were versions of the processor below 1W, but many features were disabled and the performance was lackluster. More problematic, the TDP for the chipset alone was 2W, which is well beyond smart phone territory and does not account for the display and other components. Two years later, Intel released Moorestown, which repartitioned the system across two chips, the Lincroft processor and the Langwell I/O hub. The 45nm Lincroft processor integrated graphics, dedicated video hardware and the memory controller on a low-power, SoC (system-on-chip) process, and the Langwell chipset moved to a vastly more modern 65nm node at TSMC. While a huge improvement, the 45nm SoC process was not tuned to the fullest extent possible. For example, it was still missing 3.3V I/O transistors, which complicated the design. Ultimately, the Z600 SKU of Moorestown made it into one or two phones, but the platform power consumption was still far too high to be a serious contender.

The recently announced Medfield platform is an entirely different story. After 4 years, 3 process technologies and 3 different designs, Intel finally has a product with power consumption that is appropriate for smart phones. The Penwell SoC integrates all the major components into a single chip, as required for smart phones and tablets. It is manufactured on Intel’s 32nm SoC process that has been optimized for power efficiency. The process includes three transistor libraries for performance logic, standard logic and always-on blocks and extremely dense SRAM macros. As an example of a new process technology optimization, the 32nm SoC process includes a transistor that has 10X lower leakage than any available at the 45nm node, which is crucial for always-on regions. In addition, the process has both 1.8V and 3.3V I/O transistors, which are necessary for integrating all the I/O into the SoC. At the 2012 CES launch, Intel announced designs wins with Lenovo and a long term partnership with Motorola (soon to be Google), dispelling any doubts about Intel’s ability to enter the market. Additional customers are likely to be announced at the upcoming Mobile World Congress in Barcelona.

The fact that Medfield is viable for smart phones is a testament to what Intel can accomplish when manufacturing and design are aligned. The struggle over the previous 4 years highlights the roadmap thrash, as Intel’s design teams were able to shift to new targets much faster than the manufacturing group. However, this transformation is hardly complete. The first 32nm products from Intel shipped in late 2009 and were launched to consumers in January, 2010 at CES. Phones based on the 32nm Medfield are expected to arrive in the second quarter of 2012. This is a full two years behind 32nm mainstream x86 products, and slightly behind the availability of Intel’s 22nm Ivy Bridge. Longer term, Intel intends to take advantage of the latest process technology for mobile phone SoCs, which should lag the mainstream by 6-9 months, rather than 24.

Figure 1. Medfield Platform Architecture, provided by Intel

This article examines the overall SoC architecture of Medfield, as shown in Figure 1. Each of the major SoC components, such as the CPU core or GPU could easily be the subject of an in-depth report. However, that is beyond the scope of a discussion of Medfield and also somewhat redundant, as many SoCs share licensed IP blocks. This article strikes a balance by discussing the key SoC blocks in moderate detail, but without in-depth microarchitectural examination. We conclude with an analysis of the performance and power efficiency and the implications for Intel’s aspirations in smart phones.

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