ISSCC 2006: IBM PowerPC 970MP

Figure 1 - Die Photo of PPC970MP

On February 6, 2006, IBM disclosed technical details on its new 90 nm PowerPC 970GX and the dual core PowerPC 970MP processor at ISSCC 2006 in San Francisco. Figure 1 shows the die photo of the dual core PowerPC 970MP processor. Figure 1 shows that the PowerPC 970 MP consists of identical but mirror reversed copies of a single processor core and shares the system interface between the two processor cores.

Table 1 - Implementation Details of PPC970MP and PPC970GX in 90 nm SOI

Table 1 shows the process, power, and estimated performance characteristics of the PowerPC 970MP and PowerPC 970GX processors. Interested readers will note that although the performance characteristics of the PowerPC 970MP processor operating at 3 GHz was reported in Table 1, the power consumption characteristic of the PowerPC 970MP processor operating at 3 GHz was not similarly reported. However, assuming that the PowerPC 970MP and the PowerPC 970GX processors operate at the same voltage in the 1.6~1.7 GHz range, the typical power consumption characteristic of the PowerPC 970MP processor can be estimated as approximately 160W.

The PowerPC 970MP and PowerPC 970GX processors are mainstream successors to the PowerPC 970 line of processors, and no substantial changes were made to the microarchitecture of the PowerPC970 processor line. However, the presenters from IBM did reveal an interesting footnote in the implementation of the PowerPC 970MP and PowerPC 970GX processors. The technical presenters from IBM revealed that the basic design of the PowerPC 970MP and PowerPC 970GX processors had already been completed when IBM’s process engineers reported that their most recent stress engineering work had managed to increase PMOS I_dsat transistor drive current by upwards of 32%. Unfortunately, the dramatic increase in PMOS performance means that the entire design had been pushed off of an optimal design point in terms of the ratio of PMOS versus NMOS transistor sizes. IBM’s circuit and design engineers then sought to re-dress the imbalance without a complete re-layout and re-design of the processor. The presenters from IBM revealed that tools and techniques were developed to identify specific circuits that would benefit from greatly improved NMOS performance to match the greatly improved PMOS performance. Consequently, changes were made to some SRAM circuits while register files and dynamic circuits remained unchanged. IBM reports that with these minimal design changes made at a late stage, the maximum frequency of the processor increased by 6% at a constant power envelope.