ISSCC 2006: AMD Opteron

Table 1 - Implementation Details of Various Opteron Processors in 90 nm SOI

On February 6, 2006, in the session devoted to Microprocessor implementations at ISSCC 2006, AMD disclosed details on its new 90 nm dual core Opteron processor with integrated DDR2 SDRAM memory controllers, popularly known as the F stepping. Table 1 shows the implementation details of this new Opteron processor. The new Opteron processor is a fairly power efficient device that fits within the same 95W power budget, albeit a slightly larger device, as compared to previous generations of Opteron processors. In contrast to Intel’s use of only high V_t transistors in the server-oriented Tulsa processor, AMD’s process engineers provided three different types of transistors to its design engineers, and AMD’s design engineers deployed all three types of transistors in the new processor to separately optimize for speed and power consumption. AMD reports that 90% of the transistors in the new Opteron processor are high V_t transistors, 9% of the trasistors are regular V_t transistors, and only 1% of the transistor are the high speed, but leaky low V_t transistors.

Figure 1 - Shmoo Plot

Figure 1 shows the schmoo plot for the new dual-core processor from AMD. Figure 1 is normalized to the base characteristics for the processor revealed at ISSCC 2006 - 2.6 GHz, 95W and 1.35V. The presenter from AMD reported that the legal department at AMD asked that the units used on the schmoo plot be normalized for presentation at ISSCC. However, since the operating condition of the normalizing base is reported along with the shmoo plot, Figure 1 can be readily de-normalized as needed.

Figure 2 - Die Photo of Dual core Opteron with DDR2 Controllers