ISSCC 2006: Thyristor Based Cache Alternatives

At ISSCC 2006, presenters from T-RAM Semiconductor Inc. discussed a memory technology using thyristor bit cells that aims to replace high speed SRAM in high performance processors and discrete applications. Thyristors are also known as Shockley Diodes, and use a PNPN junction structure which conducts in a single direction. This PNPN structure is well known as the basic circuit that causes latchup in bulk CMOS devices. T-RAM Semiconductor Inc. proposes to use a modified thyristor cell as a memory storage element, and argues that the performance and size of the thyrister bit cell make it a viable alternative to SRAM for use as high speed cache in high speed processors. Figure 1 gelow shows the basic PNPN device structure of a thyristor cell.

Figure 1 - Basic PNPN Structure of the Thyristor Device Structure

Figure 2 below shows T-RAM Semiconductor Inc’s implementation of the thyristor device structure in Freescale’s 130nm SOI process. Note that T-RAM Semiconductors Inc’s Thin Capacitively Coupled Transistors (TCCT) use the buried oxide layer (BOX) in the 130 nm SOI process as the insulation layer that isolates the PNPN structure from the bulk CMOS substrate.

Figure 2 - Implementation of the Thin Capacitively Coupled Transistor on 130 nm SOI Process

T-RAM Semiconductor asserts that although the demonstrated TCCT cell structure relies on the BOX layer for circuit isolation, they are investigating using thyristor cells in bulk substrates. T-RAM expects that it will soon be able to publish conference papers to demonstrate the implementation of Thyristor memory on a bulk CMOS process.

Table 1 - Cell Size Comparison of Thyristor RAM to SRAM

Table 1 compares T-RAM Semiconductor’s Thyristor cell sizes to SRAM cell sizes on comparable process nodes. T-RAM’s thyristor cell sizes are roughly one-quarter that of SRAM cells on comparable process nodes. T-RAM Semiconductor asserts that the thyristor memory storage element is able to achieve the small cell size without sacrificing read or write speeds. T-RAM semiconductor states that read and write cycles on the thyristor cells in the 130 nm test chip can be performed in 1.6 ns and 2 ns, respectively. The TCCT cells are not static memory and require an occasional injection of current into the P-base to regenerate current for the stored data. T-Ram describes this 'restore' operation as similar in spirit to the refresh action in DRAM devices. However, unlike refresh in DRAM devices, the restore operation can be completed in 500 ps - a time period far smaller than the read or write cycle. Consequently, the restore operation can be integrated into the access protocol and completely hidden in a read or write cycle.

In the presentation on the TCCT, T-RAM Semiconductor discussed the various advantages of the TCCT cell (primarily the small die size) as compared to the SRAM cell. However, there are some drawbacks that may limit the adoption of thyristor based memory storage cells as SRAM replacement in high speed memory applications. One drawback to the TCCT cell is that the fabrication of the bipolar structure does require additional process steps. T-RAM states that the TCCT test chip was fabricated on the standard 130 nm high performance SOI process from Freescale with 16 additional process steps added. However, T-RAM argues that most of steps are simple implant-only steps, and the same mask set is used for several of the additional processing steps. Moreover, the additional processing steps are all relatively simple, low-temperature steps in the backend, and do not impact the (MOS) transistor stack formation.

A second drawback that could potentially limit the adoption of the thyristor cell is that thyristor memory are rather susceptible to soft errors caused by single event upsets (SEU), just like SRAM cells. The SEU tolerance characteristics of the Thyristor structure is an interesting topic due to the fact that a SEU can inject a current pulse into the P-base and mimic the write pulse of the write cycle in the Thyristor. In response to questions about the SEU tolerance characteristic of the thyristor structure, T-RAM Semiconductor states that results from the 130nm thyristor test chip shows similar to slightly better tolerance to alpha and neutron particles as compared to SRAM on comparable 130 nm bulk processes. They also add that simulations project that SEU tolerance of the thyristor device structure should improve compared to SRAM on bulk processes. The SEU tolerance of the thyristor cell structure on a SOI process is compared to SEU tolerance of SRAM cells on bulk CMOS processes because T-RAM’s focus is currently high end embedded processors and controllers on bulk CMOS processes. The comparison of the SEU tolerance characteristics of the thyristor cell structure versus SRAM cells on equivalent SOI processes awaits further study.