Pat Gelsinger Speaks at Stanford

Today, I had an opportunity to listen to Pat Gelsinger speak at the Stanford Computer Systems Colloquium, or EE380. The seminar is held weekly and has hosted a number of interesting presenters, including Bob Colwell, Andy Glew, and Andreas Bechtolsheim.

Pat’s talk was titled "Into the Core...", and focused, to some extent, on Intel’s new microarchitecture. However, there were only two bits of information to add to what we previously described. Pat specifically mentioned some performance numbers for memory disambiguation. According to him, moving loads ahead of stores can up to 20-25% on some workloads. Since he is not (by own his own admission) an architect, these numbers should come with a grain of salt. That being said, Pat is known for an impressive memory; he cited the precise number of transistors for two Intel CPUs off the top of his head. The 25% mark seems like a good upper bound, and the average is probably in the 15-20% range. He also gave some rough figures for how well macro-op fusion (i.e. combining x86 instructions) and micro-op fusion (combining uops) work. Apparently, those two techniques combined make the CPU effectively 40% wider in some situations, which is a very impressive gain in IPC, even if the average is lower.

Although not directly related to Core, Pat did confirm that multithreading will return in future designs. This should come as no surprise, given his pronouncement that ‘braniacs’ are the future of microarchitecture.

The more interesting aspect of the talk was about general trends in the industry. Pat described several issues that will face all digital semiconductor companies; we will not discuss all of them here, but a few deserve to be mentioned. The first topic he touched on was performance and compatibility. His personal rule of thumb is that new technologies, that cannot leverage prior successes, take around five years to establish themselves. This has to do with the development cycles for the hardware and software ecosystems, and general issues surrounding the adoption of new technology. Any new technology must have an advantage over the status quo, in order to succeed in the market. Taking into account this five year adoption period, a new technology should have a 10x performance improvement over existing alternatives to survive. While this is hardly an ironclad law for all technology, it may prove to be a good litmus test for specific instances, such as co-processors.

A more manufacturing specific problem he addressed was the impact of variability on process scaling. The causes of variability are beyond the scope of this article, but the results are easier to look at. As one example of particularly bad variability, there was a graph, reproduced below as Figure 1 that shows a leakage versus frequency curve for one of Intel’s 130nm devices. Generally, leakage tends to increase with frequency, but Figure 1 shows exactly how bad the problem is.

Figure 1 – Leakage versus Frequency for a 130nm Device

The diagram indicates that reducing the top frequency by 10-15% can cut leakage in half. Since the relationship is non-linear, this means that engineers have to constrain their pursuit of frequency to keep leakage under control. Unfortunately, this variability is a problem that is not going away and will continue to get worse. Hence the solution is to balance the three goals (yield, power and frequency) across the entire design process rather than just aiming for the highest frequency and hoping for the best.

However, variability is much more insidious than simply causing lots of leakage, it also significantly reduces the reliability of devices. At larger geometries, such as the 250nm node, the probability of soft errors (i.e. transistors switching incorrectly) is relatively inconsequential. As Figure 2 below shows, this is not the case for 32nm and beyond (and even 45nm is dicey).

Figure 2 – Soft Error Rates versus Process Size

Ultimately, the only answer to this problem is to learn how to design reliable systems without assuming that the underlying parts function correctly. Initially, this may just look like business as usual; more and more parts of every chip will use parity and ECC protection, perhaps new materials such as silicon-on-insulator will become prevalent. Eventually though, changes will be required.

While only dropping a little new information about future products, such as Core and its successors, Pat’s EE380 talk was quite interesting. We certainly encourage our readers to watch the video themselves and explore some of the ideas presented. Recorded sessions from EE380 can be found at the course website, and the slides are usually online as well.