Intel's Caneland Platform Launch

Earlier today, Intel cleared away the last vestiges of the Pentium 4, and launched the first Xeon MP to use the Core microarchitecture, codenamed Tigerton. While most of Intel’s mainstream MPUs quickly transitioned to the newer microarchitecture, Xeon MP products have always lagged their cousins by a year or so. This is due to a combination of several factors. First of all, four socket MP platforms require much more thorough validation than two socket DP systems because the state space (and hence things that can go wrong) is at least twice as large. Second, many Xeon MPs are heavily modified variants of the ‘mainstream’ MPUs, with extra cache, or different transistors, which requires substantial engineering resources and additional time.

Tigerton is extremely similar to existing Intel quad-core products. It is implemented as a multi-chip package that contains two dual core 2.93GHz chips, with a total of 8MB L2 cache and a 1066MHz front-side bus. The Clarksboro chipset which accommodates Tigerton is a distant relative of the Blackford chipset. The northbridge has 4 front-side bus ports, so that each processor gets a dedicated 8.5GB/s of data bandwidth. Clarksboro is equipped with a snoop filter capable of indexing 64MB of cache, which will dramatically reduce the bandwidth used on each bus for remote snooping. The memory controller provides 4 channels of FB-DIMMs, with a maximum of 32 DIMMs for the entire system. The net result is that Tigerton and Clarksboro provide between 50-150% higher performance than the previous generation.

The power and thermal picture also changes a bit for Intel with the newer Caneland platform (Caneland is the combination of Tigerton and Clarksboro). Tigerton comes in several TDP bins, a 2.93GHz at 130W, 1.6-2.4GHz at 80W and a 1.86GHz at 50W – the latter is targeted at blade servers. There are also two dual core variants that run at 2.93 and 2.4GHz in the 80W bin. The previous top bin for Tulsa was 150W, so off the top, Intel is saving at least 80W of thermal head room. Of course, the chipset is more power hungry than its predecessor, consuming 47W, a 15W increase. However, the shift to FB-DIMMs has a more complicated impact. Intel’s Xeon MP platforms previously used 4 XMBs (eXtended Memory Bridges), each one dissipating around 12W. With newer FB-DIMM based systems, XMBs are no longer needed, saving 48W, but every FB-DIMM uses up an extra 4-6W for the AMB. So for systems with 8 or DIMMs, a bit of power is saved by the transition from XMBs to FB-DIMMs, while more populated systems will end up consuming more power overall.

Overall, the Caneland platform is a welcome additional to Intel’s product portfolio, as it completes the conversion to the Core microarchitecture and provides a significant performance boost. In fact, this is the first time in the 4 years since the introduction of the Opteron that Intel will be able to claim a decisive lead over AMD’s high-end server offerings. On average the Caneland platform will reduce the power and thermal demands between 30-70W versus the prior generation.

The bottom line is that Intel’s MP servers will be attractive to OEMs and end-users in a way they haven’t been for a long time. Intel should continue to have a sizable performance advantage until AMD can mass produce Barcelona at around 2.6GHz or higher. This will probably give Intel a 6-9 month window to make market share gains at the high-end before AMD is able to achieve (or exceed) performance parity. Hopefully, once Barcelona ramps, Intel and AMD will bring a level of competition to the MP server market that has been absent for the last several years.