IDF in Review
| 09-27-2007Intel’s Developer Forum is usually an occasion for a variety of announcements about the future of microprocessors and computing in general – and this year was no exception. The first day of IDF featured several key announcements pertaining to Penryn, Larrabee, Nehalem and Intel’s 32nm process.
Penryn
As expected, Intel announced that they will launch products based on the Penryn family on November 12th – just in time to get new systems sold towards the end of Q4. While Penryn is a derivative of the Core 2 microarchitecture, it does feature some improvements, which have been previously described. Overall, the performance for Penryn products should be slightly more (~5-10%) than the previous generation, except for certain workloads which benefit from the new SSE 4.1 instructions or the new shuffle or divider units where the improvement will be more pronounced. The power consumption for 45nm parts at the same frequency will be much lower, both due to a new low power C6 sleep state and the lower leakage transistor stack.
For HPC systems and workstations, Harpertown comes with the new Seaburg chipset. Seaburg implements a faster 1.6GHz front side bus, multiple x16 PCI-E gen 2 lanes and a more advanced snoop filter that reduces the number of cache line evictions. Several websites have previewed the new Harpertown systems, and we have our own in the works.
Nehalem
The most important news out of IDF was not the impending launch of Penryn based, but the demonstration of a fully functional two socket Nehalem system. The first stepping (A0) of Nehalem returned from the fab roughly four weeks ago, and Intel had a demo of the system booting Windows XP and running a 16 threaded workload.
It is not unusual for A0 silicon to boot Windows; Penryn A0 did as well. However, Nehalem is an incredibly complex and risky design, which makes it a more impressive accomplishment. Nehalem uses a brand new system architecture that Intel calls QuickPath: an integrated DDR3 memory controller and CSI links between processors. The processor microarchitecture itself is different from the previous generation, with four integrated cores, a shared last level cache and undoubtedly several other currently undisclosed features. Nehalem implements Simultaneous Multi-Threading, which while simple to implement is extremely taxing to validate and verify. SMT required two years of additional validation and testing before it could be enabled on the Pentium 4. The bottom line is that Nehalem was a risky design in many ways, and booting Windows (even if it was Windows XP, rather than a server OS) is a testament to the skill and talent of the Hillsboro team and the folks that worked on CSI.
Post-silicon validation takes ~12 months for high performance microprocessors. Barring any showstopper bugs, this implies that Nehalem could debut as early as August of 2008, just in time for the next IDF in San Francisco. The DP server variant of Nehalem will be the first to market, with the mobile and desktop versions following in 2009. While the DP variant of Nehalem will be aggressively pushed, the desktop and mobile versions will trickle into the high-end of the market, rather than ramping across all price points. Spring IDF in Shanghai will probably have an update about Nehalem’s microarchitecture and also the scheduled roll-out across the mobile, desktop and server product lines.
32nm Test Chip and Larrabee
While Nehalem was important, it wasn’t the only interesting wafer to return from the fab. Intel also demonstrated a 32nm test chip containing the usual SRAM arrays and various test circuits. Typically, test chips arrive about a year before first silicon, and two years before a product can actually ship. The chart below shows the timing and density of Intel SRAM test chips from the 180nm to the 45nm node.
Figure 1 - Test Chip Milestones for Intel Process Technologies
Intel also admitted in public what everybody knows – that the Larrabee design team is working on a multi-core x86 with vector extensions for graphics, codenamed Larrabee. Larrabee is intended as a coprocessor for HPC applications, and discrete graphics using ray tracing. Although some details concerning the microarchitecture have leaked, quite a bit has yet to be documented accurately.
Intel’s IT – Pathfinding for Future Platforms
One of our more interesting discussions at IDF was with Prasad Rampalli, who is a VP within the Digital Enterprise Group and was previously a VP in the IT group. His group is currently working on projects to understand the pain points for IT departments, and how Intel can effectively address these needs. By identifying challenging business processes, they hope to come up with candidates for future platform technologies that can effectively be marketed, in the same vein as vPro or Centrino. This is a logical exercise in internal testing and vetting; if a platform solution can effectively solve problems for Intel, then it at least stands a chance of succeeding in the market place. While the results of these internal projects won’t be visible for a few years, they may give IT departments something to look forward to in the future.
Summary
This IDF was a mix of extremely interesting, but expected announcements about various Intel products and technologies. The blend of news touched on most aspects of Intel's business, and even some nascent products, such as Larrabee, WiMAX and ultra-mobile designs. The overall picture is that Intel continues to execute quite well, with a strong product roadmap. Ultimately, this is the result of Intel employees and management regaining a healthy dose of Andy Grove's famous paranoia and we hope that this will continue far into the future.
