Our previous website was a fully custom Cold Fusion application that incorporated both a primitive Content Management System (CMS) and a very active threaded forum. As with most Cold Fusion applications, the back-end was Microsoft SQL Server. One of the biggest challenges with our old website was adapting to the rapid pace of change on [...]
We’d like to welcome everyone to the latest and best incarnation of Real World Tech (RWT). RWT started 16 years ago and has grown to become one of the leading venues for deep technical analysis of the computer and semiconductor industries. Over the years, the internet has evolved considerably and our new website design is [...]
The Ivy Bridge GPU takes advantage of Intel’s 22nm FinFET process to nearly double performance and enhance programmability with DX11 and OpenCL 1.1 support. The new scalable architecture features more powerful shader cores, distributed sampling pipelines, a high bandwidth L3 cache, tesselation and 4K resolution displays. Overall, Ivy Bridge should be the highest performance integrated GPU at launch and Intel’s first competitive graphics offering.
In our Sandy Bridge-EP and Romley platform review, we look at the performance and power efficiency gains for Intel’s latest server microprocessor on industry standard benchmarks including SPECcpu2006 and SPECpower_ssj2008. The results are impressive, Sandy Bridge-EP is clearly the best x86 server processor on the market, and Romley will be the platform of choice for the next 2 years.
Our first look at Kepler focuses on architectural changes to the shader core that emphasize graphics performance and the enhanced power management. Based on our analysis of Nvidia’s 28nm GPU strategy, we project a new shader core for throughput computing products and discuss the expected features.
Sandy Bridge-EP is the first major overhaul for Intel servers since 2009, and nearly ever aspect has been enhanced. The processor pairs 8 cores with a large last level cache, DDR3 memory controller, QPI 1.1, integrated PCI-E and power management. This article provides an overview of the major features, including new I/O optimization and power capping techniques and discusses the expected impact.
Intel’s upcoming Haswell microprocessors include transactional memory and hardware lock elision that are exposed through the Transactional Synchronization Extensions or TSX. In this article, I discuss TSX and predict the implementation details of Haswell’s transactional memory and expected adoption across the industry, based on my previous experience.
AMD’s new management took to the stage to highlight a new strategy and share the roadmap for 2012-2013. The executives generally came across well and there are only a few changes from the existing focus, with no major shifts. The updated server roadmap seems challenging, given the competition, but client systems should do decently and expand AMD’s footprint in mobile.
For 4 years, Intel has struggled to move into the market for mobile devices. Conventional wisdom holds that x86 is too inefficient for smart phones. The recently announced 32nm Medfield proves that x86 is a viable option and that Intel can design smart phone products. We explore the Medfield SoC and analyze the impact on Intel’s mobile strategy.
IBM’s mainframes are the oldest line of computers, dating back to 1964 and occupy a special place as the world’s first instruction set architecture. This longevity and extreme backwards compatibility are responsible for perhaps the most lucrative computer franchise. IBM’s z196 is the first mainframe with an out-of-order CMOS microprocessor, and also the first with an integrated L3 cache. These two innovations are largely responsible for a 30-40% improvement in performance over the previous generation z10.