Announcement of the IBM PowerPC 970 Processor

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In the first presentation of the PC processors session, IBM presented details of its new PowerPC compatible processor, the PowerPC 970. The PowerPC 970 processor is a new processor designed for the desktop and small scale server market. The core of the PowerPC 970 processor is based on the high performance POWER4 processor core. The POWER4 processor was targeted toward the high end server market, and the configuration as well as the cost of the processor package ensured that the processor as unsuitable for the smaller server or desktop workstation market. The PowerPC 970 was designed to provide coverage and garner design wins from this market segment.

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Although the PowerPC 970 is a part that would cost considerably less to manufacture and sell, its performance actually exceeds the POWER4 processor in many areas. The reason for this apparent paradox is that the POWER4 processor had been designed for the high cost, continuous availability server market, and in some areas, performance had been traded off to obtain near-absolute reliability guarantees. As an example, in an article published in Microprocessor Reports in 1999, IBM described its use of thicker gate oxides in the POWER4 processor to obtain a failure rate that is two orders of magnitude better than comparable processors from most other manufacturers. The cost of the thicker oxides is the reduced drive current of the transistor and consequently slower switching speed of the transistors on the POWER4 processor. In the case of the PowerPC 970, the processor does not need to meet similar reliability requirements as the POWER4 processor, and as a consequence, circuit and process technology can be tweaked to obtain higher performance by trading away the near-absolute reliability required by the POWER4 processor.

In figure 1, we show rough block diagrams of the PowerPC 970 processor and compare it against the POWER4 processor. Figure 1 shows that one CPU core from the dual CPU core POWER4 processor is removed, the size of the L2 cache was resized to 512KB and optimized to connect to the single CPU core. A Vector SIMD unit was also added to the processor to handle the vector SIMD instruction extensions, and a new bus interface unit has been implemented to optimize for low cpu-count system performance.

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