RISC vs. CISC Still Matters

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In the early 1980s the computer industry was gripped by a great new idea. It was called Reduced Instruction Set Computing, or RISC, an acronym coined by David Patterson, a computer architecture researcher and professor at the University of California at Berkeley. The term originally applied to the concept of designing computers with a simplified and regular instruction set architecture (ISA) that could be implemented efficiently with minimal overhead (control logic) and be amenable to such performance enhancing techniques as instruction processing pipelining and high processor clock rate.

In addition, the ISA would be deliberately designed to be an efficient and transparent target for optimizing compilers. In fact the compiler would be a crucial element as it absorbed various vital but complex and burdensome functions traditionally supported in hardware, such as synthesizing complex program functions and addressing modes from sequences of the more elementary arithmetic and logic functions directly performed by digital circuitry. Unlike most earlier computers, RISC architects fully expected their progeny would only be programmed in high level languages (HLLs), so being a good compiler target was the goal rather than being conducive to assembly language programming.

The primary commandment of the RISC design philosophy is no instruction or addressing mode whose function can be implemented by a sequence of other instructions should be included in the ISA unless its inclusion can be quantitatively shown to improve performance by a non-trivial amount, even after accounting for the new instruction’s negative impact on likely hardware implementations in terms of increased data path and control complexity, reduction in clock rate, and conflict with efficient implementation of existing instructions. A secondary axiom was that a RISC processor shouldn’t have to do anything at run time in hardware that could instead be done at compile time in software. This often included opening up aspects of instruction scheduling and pipeline interlocking to the compilers code generator that were previously hidden from software by complex and costly control logic.

By the mid-1980’s the benefits of RISC design principles were widely understood and accepted. Nearly every major computer and microprocessor vendor developed new processors based on the RISC principles and the resulting designs were all remarkably similar. These ISAs had large general purpose register files with 32 addressable registers (one of which always read as all zeroes), uniformly sized instructions 32-bits in length, few instruction formats, only one or two addressing modes, and complete separation between instructions that compute and instructions that access memory (loads and stores). Soon the term RISC became synonymous with computer designs that shared some or most of these attributes.

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