Editor’s Note: This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, all with permission of the author. Introduction The VAX was an orthogonal, 32-bit CISC instruction set […]
Introduction The 2005 International Electron Devices Meeting (IEDM) was held in the Hilton Hotel on Connecticut Ave in Washington DC from December 4 through December 7. In the four day period, 1800 attendees from all over the world listened to and examined materials presented on the state of the art in the field of semiconductor […]
This article discusses three problems facing modern high performance MPU architects: decreasing returns from ILP, increasing power dissipation and relatively constant interconnect performance.
Partial coverage of IEDM 2003 Day 2, focusing on AMD and Intel process technologies
Paul discusses the history and future of x86, with an eye towards its potential successors
Part 2 of Paul’s investigation into CMOS, the device that has literally made the microprocessor industry
An in depth look at the FO4 metric used to validate circuit designs in microprocessors.