Computational Efficiency in Modern Processors

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The computer industry is on the cusp of yet another turn of the Wheel of Reincarnation, with the graphics processor unit (GPU) cast as the heir apparent of the floating point co-processors of days long gone. Modern GPUs are ostensibly higher performance and more power efficient than CPUs for their target workload, and many companies and media outlets claim they are leaving CPUs in the dust. Is this really the case though? This article explores the quantitative basis for these claims, with some surprising results.

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Hot Chips XXI Preview

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Hot Chips 21 is nearly upon us, and with it comes updates from the major processor vendors and players in the PC industry and beyond. Key themes this year include CPUs, chipsets, FPGA and GPU co-processors and academic parallelism research. Our preview will briefly discuss and analyze some of the more interesting topics, with CPU highlights including AMD’s Magny Cours, Fujitsu’s SPARC64-VIIIfx, IBM’s POWER7, Intel’s trifecta of Moorestown, Beckton/Nehalem-EX and Westmere, and Rainbow Falls from Sun. In the broader ecosystem, there will be presentations on OpenCL, Ion from Nvidia, TI’s OMAP SOC for mobile phones, and three major parallelism labs – Berkeley, Illinois and Stanford.

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ISSCC 2008 Preview: Silverthorne, Rock, Tukwila and More

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This article presents a preview of ISSCC 2008, including discussion of Intel’s Itanium processor, codenamed Tukwila and an ultra-low power x86 MPU codenamed Silverthorne. Other presentations include Sun’s Rock and Niagara 3 processors, the 45nm CELL processor and assorted DRAM and SRAM prsentations.

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ISSCC 2007: A Brief Survey

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David Kanter reports on several presentations from ISSCC 2007, including ones covering PA Semi, Intel’s Merom/Core 2 Duo, Niagara II and NEC.

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Niagara II: The Hydra Returns

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History of Niagara Two years ago at Hot Chips 16, Sun Microsystems disclosed Niagara, an innovative microprocessor and system design that represented a radical departure from traditional computer architectures. The roots of Niagara lie in Hydra, a research project under Professor Kunle Olukotun that was working on chip multiprocessing in the late 1990’s. The Hydra […]

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A Historical Look at the VAX: DEC, NVAX, Alpha and Competitors

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A Historical Look at the VAX: DEC, NVAX, Alpha and the Competition [Part II] Editor’s Note and Introduction: This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, […]

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A Historical Look at the VAX: Microprocessor Economics

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Editor’s Note: This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, all with permission of the author. Introduction The VAX was an orthogonal, 32-bit CISC instruction set […]

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The Battle in 64 bit Land: Merchant Chips on the Rise

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This is the fourth article in a series that that started in 2000 with The Looming Battle in 64 bit Land, followed by The Battle in 64 bit Land Revisited in 2001, and The Battle in 64 bit Land, 2003 and beyond in 2003.

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The Battle in 64 bit Land, 2003 and Beyond

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Paul updates his analysis of the 64-bit computing landscape for 2003.

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Looking Forward to 2002

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Paul DeMone takes a look at what significant events may occur in the MPU market in the coming year.

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