AMD’s Jaguar Microarchitecture

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Jaguar is AMD’s first 28nm processor, a compact 3.1mm2 design that targets 2-25W devices. It is a derivative of the earlier 40nm Bobcat, a fully out-of-order two issue design, with significant improvements in instruction set architecture and implementation. Some of the highlights include support for AVX, wider 128-bit datapaths, and a higher performance L2 cache. Jaguar is already shipping in several AMD SoCs targeted at tablets, notebooks, microservers, and desktops. However, it is far more prominent as the CPU powering the Sony Playstation 4 and Microsoft Xbox One.

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Silvermont, Intel’s Low Power Architecture

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Silvermont is Intel’s first CPU core tailored for power efficient applications such as smartphones, tablets, and microservers. The 22nm microarchitecture features updated instruction set extensions, full out-of-order execution with a tightly coupled L2 cache, aggressive power management, and a new high performance SoC fabric. These enhancements deliver tremendous performance and frequency gains over the aging Atom core, putting Intel’s mobile strategy in a more competitive position.

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Lessons in Technology and Innovation from the iPad 3 Graphics and Display

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The iPad 3 was an influential and successful tablet, but an excellent example of an unbalanced system. In particular, the superb Retina display was not adequately matched by the GPU of the A5X, and represented a step backwards in terms of graphics capabilities. This article explores the challenges of designing innovative products given the underlying technical constraints, through the lens of the iPad 3 and its successors.

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Intel’s Haswell CPU Microarchitecture

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Intel’s Haswell CPU is the first core optimized for 22nm and includes a huge number of innovations for developers and users. New instructions for transactional memory, bit-manipulation, full 256-bit integer SIMD and floating point multiply-accumulate are combined in a microarchitecture that essentially doubles computational throughput and cache bandwidth. Most importantly, the microarchitecture was designed for efficiency and extends Intel’s offerings down to 10W tablets, while maintaining leadership for notebooks, desktops, servers and workstations.

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Intel’s Near-Threshold Voltage Computing and Applications

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Near-threshold voltage computing extends the voltage scaling associated with Moore’s Law and dramatically improves power and energy efficiency. The technology is superb for throughput, at the cost of latency, and best suited to Intel’s products for HPC and mobile graphics.

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ARM Goes 64-bit

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The new ARMv8 architecture is classically British; a clean and elegant 64-bit instruction set, with compatibility for 32-bit software. The 64-bit mode eliminates many complicated and awkward features and will foster a larger and more diverse ARM ecosystem with new licensees and applications.

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AMD’s Analyst Update

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AMD’s new management took to the stage to highlight a new strategy and share the roadmap for 2012-2013. The executives generally came across well and there are only a few changes from the existing focus, with no major shifts. The updated server roadmap seems challenging, given the competition, but client systems should do decently and expand AMD’s footprint in mobile.

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Medfield, Intel’s x86 Phone Chip

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For 4 years, Intel has struggled to move into the market for mobile devices. Conventional wisdom holds that x86 is too inefficient for smart phones. The recently announced 32nm Medfield proves that x86 is a viable option and that Intel can design smart phone products. We explore the Medfield SoC and analyze the impact on Intel’s mobile strategy.

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AMD’s Mobile Strategy

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With all the recent changes, AMD seems like a ship adrift at sea with no clear strategy or vision. We look at AMD and where they are likely to head in the coming years for tablets and phones and explain why they will stick with x86, rather than embrace ARM as some have suggested.

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ISSCC 2012 Preview

Highlights of the upcoming 2012 ISSCC include the first 22nm disclosures from Intel and several SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu on system level power for the K supercomputer.

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