Rambus Sets the Bandwidth Bar at a Terabyte/Second
Last week at the annual Developer’s Forum in Japan, Rambus announced an ambitious technology initiative that aims to create a 16 gigabit-per-second memory signaling layer that can sustain 1TB/s of bandwidth to a single memory controller by 2010. The Terabyte Bandwidth Initiative is still in development hence there are no shipping products, but the goals are now public and Rambus will demonstrate a test board that achieves 1TB/s of bandwidth over this signaling technology. This article will provide an in-depth look at the history, target market, technical innovations and test vehicle for Rambus’ Terabyte Bandwidth Initiative (TBI).
The target markets for Rambus are the segments of the DRAM market that prefer high bandwidth and are willing to sacrifice capacity to achieve that bandwidth: graphics, consoles and possibly networking. Graphics almost universally uses GDDR3 or GDDR4, with GDDR5 slated for 2H08. Consoles use GDDR and XDR (in the case of the PS3), while networking applications use DDR, SRAM and RLDRAM (Reduced Latency DRAM).
Several trends within the computing industry have driven a tremendous increase in the need for high bandwidth memory systems. The exponential increases in graphics performance and display capabilities require exponentially faster memory. The fierce competition between NVIDIA and ATI for graphics performance is typified by extremely fast product cycles. Each new product from either one of the contenders contains a greater number of programmable pipelines, operating at a faster frequency as well. The graphics memory must increase proportionally in order to feed the highly parallel graphics processors. On the display side, resolutions increase to match the capabilities of graphics processors, and the internal frame buffers must be fast enough to transfer 30-60 frames per second.
Multi-core processors have had a similar (although less extreme) impact on the general purpose market. In theory, a dual core processor needs twice the memory of a single core processor, the reality is that processor architects typically use cache to reduce the demand on the memory subsystem. While processors do not require quite the same bandwidth as graphics applications, the mismatch between execution capabilities and memory bandwidth (which is often referred to as the Memory Wall) is growing quite fast. In 1989, the 486 ran at 16-25MHz, with 8KB of on-die cache and used 33MHz memory. In 2007, a Core 2 Duo based processor features 2-4 cores running at 3GHz, with 6-12MB of cache and uses two channels of 1.33GHz DDR3 memory.
These trends are also found in the gaming console market. Consoles require both general purpose and graphics processors, with matching high performance memory hierarchies. Figure 1 above shows the bandwidth used by various gaming consoles from 1985 to 2006, and Rambus’ target: 1TB/s in 2010.
Figure 1 – Bandwidth Trends in Gaming Consoles
The 1TB/s target was calculated by looking at the overall trend (10X increase every 5 years, 50GB/s in 2006), and then doubling the extrapolation for 2010. For products to ship in that 2010 timeframe, Rambus’ IP must be fully validated and verified for high volume 45nm and 32nm processes well in advance of this target, since system designers will require time to integrate 3rd party IP.
The Rambus signaling technology operates at 16gbps, and it is envisioned that a single memory controller could connect to 16 DRAMs, with each DRAM providing 4 bytes of data per cycle (1TB/s = 16gbps * 4B * 16 DRAMs). To reach the 1TB/s target, Rambus is relying on three key techniques to increase bandwidth: 32X data rates, full speed command and addressing, and a differential memory architecture.