x86 Servers Brace for a Hurricane

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While IBM’s prowess as an MPU design house rests on recent accomplishments, notably the POWER4 and POWER5, it is unquestionable that IBM has few equals in the area of system level design. IBM’s storied history of system design dates back to the success of the S/360; today, IBM’s zSeries (the successor of the S/360) represents the zenith of high-end system architectures. Fortunately, other divisions within IBM have reaped the technological benefits of IBM’s mainframe dominance. Both Drs. John McCalpin and Tom Bradicich readily admit that their products (respectively the pSeries and xSeries systems) have been heavily influenced by techniques first perfected by mainframe architects [1][2]. It has always been exciting to see new technologies trickle down from the mainframe world, as Moore’s Law provides chipset designers with ever increasing transistor counts. This article takes an in-depth look at the basic nodes, coherency mechanisms, memory subsystem and I/O subsystem of IBM’s new X3 architecture, which was presented at IDF Spring 2005, by Dr. Tom Bradicich.

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