The Third Dimension
Modern integrated circuits are already three dimensional in nature. The various layers of interconnect tower over the transistor devices underneath, each layer of metal larger than the previous one, as shown in Figure 4 on the previous page. Yet the transistors remain in a planar configuration, only the connections between them are stacked. The innovation in the third dimension is using multiple layers of silicon substrate, each one containing transistors, arranged in a stacked configuration, one on top of the other. The interconnect wires run on top of each substrate as in conventional chips, but also tunnel directly through layers in a vertical fashion [8], as shown in Figure 5.
Figure 5 – Two layer stack, face to back, with through die vias tunneling between layers
The three dimensional integration of multiple device layers results in several advantages over the present regime. The chief benefit is that the interconnects between blocks are shorter, in some instances considerably so, as illustrated in Figure 6. This lowers power dissipation since fewer buffers and flip-flops are needed. Reducing the amount of metal that runs across the chip also reduces power dissipation. Lower inter-block latency reduces cycle time, increasing frequency and chip performance. Stacking layers also increases chip density, as more transistors are able to be placed per unit of volume and within one clock cycle of each other. Cost reduction is a byproduct of this as fewer pins are needed per chip to communicate with other nearby chips, compared to the prior arrangement, simplifying packaging.
Figure 6 – Wires running across opposite ends of planar chip can be run directly between stacked functional units, reducing millimeters of metal to micrometers
Three dimensional integration has also resulted in a reinterpretation of Rent’s Rule [9], which has traditionally been used to analyze planar integrated circuits, to better predict interconnect complexity, power dissipation, and cost for various circuit types. The final advantage of three dimensional integration is using multiple heterogeneous device layers [8] on top of each other, as illustrated in Figure 7. One logic optimized IC can be stacked on a memory optimized chip, which can itself be stacked on top of a mixed-signal IC. Traditionally, incorporating distinct types of integrated circuits (i.e. logic, DRAM, analog) requires compromising the performance of any one type of integrated circuit. The advantage of three dimensional integration is that each layer can be individually optimized for performance (however performance is defined – be it density, frequency or precision), without compromises to share the same layer. Thus the best of all these various process-optimized disciplines can be integrated in a single stack.
Figure 7 – Complete system integration with heterogeneous 3D device stack
While all these advantages are significant, the three dimensional integration also has its drawbacks. Overall power consumption is reduced since less interconnect is used; however power density can increase in parts of the 3D integrated circuit. Without careful attention early in the design and simulation of the chip, the resulting thermals could reach unacceptable levels, affecting device reliability and requiring expensive cooling solutions.
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