3D Integration: A Revolution in Design

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As interconnect scaling problems exasperate power, performance, and yield issues for current MPU designs, architects and manufacturers have sought new methods to surmount these obstacles. While certain techniques can alleviate some of the problems in the short term, they come with their own problems and are not a permanent solution for interconnect performance.

Three dimensional stacked integration presents a unique and novel solution to interconnects that promises to simultaneously improve performance, while reducing power and silicon real estate of future integrated circuits. Three dimensional stacking also permits heterogeneous layers to be integrated, each optimized for their unique functions, making novel integrated circuit applications possible. The increased density of stacked silicon designs can be achieved while mitigating device yield concerns and delivering on the promise of Moore’s Law for the immediate future.


[1] G. D. Wilk et al., “High-k gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, Volume 89, Issue 10, pp. 5243-5275
[2] D. K. Sadana et al., “Strain Engineering for Si CMOS Technology”, IBM
[3] J. Kavalieros et al., “Tri-gate transistor architecture with high-k gate dielectrics, metal gates, and strain engineering”, VLSI 2006
[4] James D. Meindl, “Interconnect Opportunities for Gigascale Integration”, IEEE Micro, vol. 23, no. 3, pp. 28-35, May/June, 2003
[5] W. Dally, “Stream Processors: Programmability with Efficiency”, ACM Queue, Vol. 2, No. 1, March 2004, pp. 52-62
[6] Nagaraj NS, et al., “Interconnect modeling for copper/low-k technologies”, 17th international conference on VLSI Design, 2004
[7] Noriyuki Ito, et al., “Diagonal Routing in High Performance Microprocessor Design”, ASPDAC 2006
[8] J. Baliga, “Chips go vertical”, IEEE Spectrum, Volume 41, Issue 3, March 2004, pp. 43-47
[9] S. Das, et al., “Calibration of Rent’s Rule Models for Three-Dimensional Integrated Circuits”, IEEE Transactions on VLSI Systems, April 2004
[10] A. W. Topol et al, “Three-dimensional integrated circuits”, IBM Journal of R&D, Volume 50, Number 4/5, 2006
[11] P. Lindner et al., “3D interconnect through aligned wafer level bonding”, Proceedings of the Electronic Components and Technology Conference, pp. 1439-1443, May 2002
[12] B. Black et al., “Die Stacking (3D) Microarchitecture”, International Symposium on Microarchitecture, 2006
[13] G. Hinton et al., “The Microarchitecture of the Pentium 4 Processor”, Intel Technology Journal Q1, 2001
[14] B. Black et al., “3D processing technology and its impact on ia32 microprocessors”, Proceedings of the IEEE International Conference on Computer Design, pp. 316-318, 2004

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