As interconnect scaling problems exasperate power, performance, and yield issues for current MPU designs, architects and manufacturers have sought new methods to surmount these obstacles. While certain techniques can alleviate some of the problems in the short term, they come with their own problems and are not a permanent solution for interconnect performance.
Three dimensional stacked integration presents a unique and novel solution to interconnects that promises to simultaneously improve performance, while reducing power and silicon real estate of future integrated circuits. Three dimensional stacking also permits heterogeneous layers to be integrated, each optimized for their unique functions, making novel integrated circuit applications possible. The increased density of stacked silicon designs can be achieved while mitigating device yield concerns and delivering on the promise of Moore’s Law for the immediate future.
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