AMD’s Griffin Flies to the Fore

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AMD’s Griffin Flies to the Fore

In 2003, AMD bet the company on a server microprocessor, the K8. This turned out to be a wise move, as servers were a key weak point in Intel’s product line-up. The K8 even worked fairly well as a desktop MPU, where the performance could justify the relatively large thermal envelope. Unfortunately, the K8 did nothing to challenge Intel’s dominance of the notebook market. In fact, certain technical decisions which benefited the K8 for servers and desktops in fact hindered adoption into the notebook market. AMD notebooks have met with modest success in the retail channels, through stores such as Best Buy or Circuit City. The higher end corporate notebooks are mostly Intel Inside due to the power and platform advantages, although Toshiba recently announced they would use AMD processors in some mid-range business user notebooks.

At the Microprocessor Forum, AMD Fellow Maurice Steinman presented Griffin, a MPU specifically adapted for the notebook market, due out in 2008. Griffin is in many ways a compromise between the improvements required to address the notebook market and AMD’s available resources (which are mostly being invested in Barcelona). One of the first decisions was to use the older K8 core, largely unchanged, with 2x1MB L2 caches. The microcode has been updated (which adds virtualization support and other enhancements), but the microarchitecture is relatively untouched, with none of the innovations from Barcelona. Not all of the improvements in Barcelona are suitable for a low power MPU anyway; while improving branch prediction is always a win, it’s not clear that a shared L3 cache is particularly useful for notebooks (especially from a die size perspective). Instead, the improvements for Griffin are largely focused on the lower level circuit optimizations and the northbridge, which are both very high leverage points.

From the circuit side, the biggest change is in the power and clock distribution. The K8 had a single PLL and a single voltage plane for the cores and northbridge. As a result, if the cores and memory controller had to be placed into a sleep state in tandem – if either one was active, the other one was as well. Many integrated graphics solutions rely on an external frame buffer that is kept in system memory and accessed at least every 1/60th of a second (and likely much more often depending on the screen refresh algorithm). Hence, the older K8 cores could not transition into sleep states, because they would be periodically woken up by the frame buffer and memory controller activity.

Like the K8, Griffin has one PLL for the cores and the northbridge, which runs at the maximum frequency. However, each core has a digital frequency synthesizer, which runs off the PLL and produces a local clock using digital dividers and pulse dropping. This local clock can change without relocking the PLL – saving time in frequency transitions. Each core will have 8 operating frequencies, and the two cores can run independently of one another. To complement this improvement, Griffin also has 3 major voltage planes (in addition to three for analog and I/O): one for each core and one for the northbridge, so that the voltages can be modified in conjunction with the frequency for the best power savings. The downside of the additional voltage planes is that the system will require additional voltage regulation modules on each board; while this increases expenses for manufacturers, it is an improvement that is certainly worth the cost.

The key point of these enhancements is that the power states for the cores are now independent of the northbridge for all integrated graphics configurations. Unlike the K8, notebook chipsets for Griffin with integrated graphics will not need external frame buffers to achieve power savings in the processor cores. This will reduce the overall cost and power consumption of the platform and addresses a problem with the previous generation.

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