AMD Aims To Take Over x86 Leadership

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So What Does a 64 bit x86 Look Like?

Calling a computer architecture ’64 bits’ means different things to different people. For a marketing person this is quite a flexible attribute and has in the past meant that a CPU has at least one data path or register in its implementation that is 64-bits wide. For computer designers, a 64 bit architecture is one that supports 64-bit general purpose registers, instructions for arithmetic and logical operations on 64 bit integers, and the ability to perform 64 bit logical addressing for pointer manipulation and array index calculation.

One way of predicting what AMD’s x86-64 will look like is to examine how the x86 was extended from 16 bit to 32 bit starting with the Intel 386 and apply the same basic principles to reach 64 bits. The basic 16 and 32-bit programmer’s model of the x86 along with one possible 64 bit implementation are shown in Figure 1. The floating point (FP) component of ISA will be dealt with later.

Figure 1

According to AMD, addressing in x86-64 will be 64-bit by default, with the option to override for 32-bit addressing. Also, x86 data manipulation instructions will default to 8 and 32-bit with the option to override for 64 and 16-bit. The x86-64 ISA specifies that the results of 32-bit operation will be sign extended to a full 64 bits before updating the target register. This is similar to what RISC designs such as 64-bit MIPS and Alpha do when executing 32 bit data manipulation instructions. Immediate and displacement fields in x86-64 instructions will be either 8 or 32-bits in length to limit code bloat, however, there will be a new instruction to load a 64-bit immediate data value into a register. AMD has said x86-64 will have “no segment base or limit registers”. This seems to indicate that the segment registers CS, DS, SS, and ES will not be used in 64 bit mode since there are no segment descriptors to select.

What’s the Floating Point?

Probably the worst feature in the x86 architecture is the floating point architecture with its eight 80-bit registers organized as a stack. Code sequences compiled to evaluate an arithmetic expression often require extra instructions to get at operands because of the stack-based computational model. The x86 stack model also needs extra instructions to preserve intermediate values when data flow analysis indicated these values can be reused later in the program.

AMD has decided to take this problem head on and change the programming model to a flat floating point register file for x86-64. Since this requires the addition of new instructions to use this new flat register file they also decided to utilize RISC-style three address FP instructions. That is, a FP instruction that takes its operands from two registers and writes back the result to a third register.

The main advantage of three address FP instructions is that it saves extra instructions that would otherwise be needed to shuffle values around the register file or make copies when the compiler wants to reuse a value or place a final result back into the register reserved for argument passing or a function return value. AMD has not stated how many FP registers x86-64 would have but it seems likely to be 16 or 32 rather than 8. Having a large number of FP registers allows a clever compiler to unroll and software pipeline the computationally intensive loops typically found in scientific and engineering type applications.

The new instructions and flat FP register file seem to only support double precision (64-bit IEEE) operations. At first this may seem surprising but technical code generally eschews single precision format data to avoid numeric problems from loss of accuracy. For 3D graphics and other FP applications that only need 32-bit single precision data the 3Dnow extensions will apparently suffice.

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