AMD’s 64 Bit Gamble

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Extending The Extension

To the eternal relief of programmers the world round, the most abrasive aspects of the x86 instruction set architecture were smoothed over in the major extension to 32 bits first delivered in the form of the Intel 386 in 1985. Unfortunately the benefits of this extension eluded most end users for nearly another decade until Microsoft shipped the first mass-market 32-bit applications and operating system. The 32-bit extension to x86 made the 32-bit extended register file look more like general purpose registers, although there was still only eight of them. More importantly, the segmentation scheme was extended in such a way that it could emulate the 4 Gbyte flat address space offered by other 32-bit microprocessors.

The 32-bit extension to the x86 architecture was performed in such a way that was backward compatible. That is, every 32-bit x86 processor from the 386 onwards could also execute 16-bit x86 code that previously ran on the 8088 and 80286. This was done with something called a mode bit. However unlike, for example, the VAX-11 mode bit for PDP-11 compatibility, the modern x86 allows intermixing of 16 and 32 bit instructions. The mode bit for a code segment sets the default operand code size for the ‘long’ version of x86 instruction encoding to either 16 or 32 bits. A special opcode prefix byte is used to override operand size of an instruction in a 16-bit code segment to 32 bits and to override the operand size of an instruction in a 32-bit code segment to 16 bits.

Although the exact details of AMD’s extension to the 32-bit x86 architecture are not known in detail, it is likely that a similar scheme is used. Some differences between the x86 extension to 32 bits and the extension from the 32-bit x86 ISA to x86-64 have been disclosed. These include optimizations that rely on the fact that 64-bit immediate data and displacements are rarely necessary and waste a lot of space. For example, 64-bit code segments default to 64-bit addressing with 8 and 32-bit data operations. Overrides (instruction prefix bits most likely) will be available to force 32-bit addressing and also operations on 16 and 64-bit data. Also, the result of 32-bit data operations will be signed extended to the full 64-bit length of the general purpose registers, while 8 and 16-bit operations do not affect the most significant 32 bits. The only 64-bit immediate value supported is for a special move immediate to register instruction.

One interesting element of x86-64 is AMD’s decision to add an instruction set extension called technical floating point or TFP. TFP introduces a RISC-like floating point computational model that combines a flat floating point register file with a set of three address, register to register, IEEE double precision floating point (FP) operations. This is an attempt to overcome one of the greatest obstacles to enhancing floating point performance in x86 processors; the antiquated stack oriented x87 instruction set architecture. AMD has not disclosed the size of the register file associated with TFP, or whether it overlaps with any of the other x86 programmer visible processor state. However, x86-64 will include full x87 functionality in addition to TFP to ensure backward compatibility with existing software. AMD hopes TFP will allow the K8 to approach the FP performance levels of high-end RISC processors. However, the wide disparity in FP performance between different RISC processor families, all with similar FP ISA models, indicates that although the TFP addition may be necessary to improve x86 performance it will not be sufficient in itself to challenge the best performing RISC processors like Alpha and PA-RISC.


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