AMD’s 64 Bit Gamble

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Dr. Jekyll and Mr. RISC

Although AMD is unable to replicate IA-64 in form, could it do it in spirit? Would a split personality CPU, perhaps implementing both x86-64 and a RISC instruction set be feasible or even desirable? Some clue of what AMD is (or might have been) planning for K8 or its successor is revealed in a recently issued AMD patent (U.S. 6,081,884), which describes a processor scheme, shown in Figure 1, that incorporates both RISC and x86 instructions within fixed length ‘long instruction words’ using predecode bits. The heart of the processor is a FIFO called the central window that buffers 360 bit long VLIW-like instruction words prior to execution. The long instruction words are actually synthesized on the fly based on the RISC and x86 instruction bytes residing in the instruction cache, along with special predecode bits that indicate the start and end of x86 instructions and optionally functional unit assignment. An unusual feature of AMD’s design is that the microcode sequencer unit can generate either a sequence of simple x86 instructions, RISC instructions, or a combination of both to implement complex x86 instructions. This is a result of the simple x86 functional units being also capable of executing RISC instructions.


Figure 1 – One Possible Suggested Organization of K8

If AMD decided to implement a bilingual x86/RISC design for the K8, an important decision is whether to design yet another new RISC architecture or license an existing one. AMD has shown in the past that it is self-confident enough not to feel the need to reinvent the wheel, so the odds are they would license an existing RISC ISA. The choice of the Alpha ISA seems obvious, as AMD has previously licensed Alpha intellectual property (IP) from Compaq in the form of bus technology for the K7/Athlon family. The Alpha is also a particularly clean and streamlined RISC ISA free of annoyances, such as delayed branches and redundant instructions, from being extended from 32 to 64 bits. As such, it would likely be the first choice by AMD’s architects and designers (many of whom are ex-Alpha designers).

However, there are at least three other explanations for the 6,081,884 patent which do not involve a full blown bilingual x86/RISC K8 design. The first is that the RISC instructions and functional units shown in Figure 1 are strictly the ‘RISC-like’ TFP floating point extensions to x86-64 previously mentioned, and all integer and memory access instructions are performed by the two x86/RISC units. A strong argument against this hypothesis is the fact that Figure 1 would imply an unusually wide capacity for issuing floating point instructions – from 60 to 100% of issue capacity. In contrast the Alpha 21264, a processor designed to perform well for FP intensive applications, can issue four integer instructions and two FP instructions per clock cycle. This would suggest the RISC units include integer processing capabilities.

The second explanation is that the RISC instructions shown in Figure 1 actually represent micro-ops (uops), and that the predecoder block actually decomposes some x86 instructions into uops. In this case, the K8 instruction cache would store a mixture of micro and macro (x86) operations. This would be a sort of hybrid scheme between the Willamette trace cache, which only stores uops, and existing x86 processors, like the P6 and K7. The third explanation is that the patent covers work that either AMD abandoned (supposedly the K8 project was scaled back to be a more of an evolution of the K7 core), or simply wrote up as a defensive patent against IA-64 to place a stake in the ground for freedom of action for the future (K9?).


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