Back to Basics – Laying the Foundation

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They Come in All Sizes and Shapes

An ISA also specifies what size and type of data formats are supported. For example, on the 32 bit x86 platform, Tthe standard data sizes are characters (8 bits), a half word (16 bits), full word (32 bits) and double word (64 bits). On a 64 bit architecture, such as Alpha or Power, a word would correspond to 64 bit, and the entire scale would shift accordingly. It is worth noting here that word and double word are used to describe integer values, while single and double precision are the equivalent terms for floating point data.

Aside from those data types, there are only a few other data formats worth mentioning; particularly IEEE 754, the standard representation for floating point data, and packed decimal, a method of storing exact decimal numbers using 4 bits to represent a single digit. Earlier, when there were more competing architectures, each family of MPUs had its own floating point format. However, eventually IEEE 754 was adopted to standardize floating point hardware in order to make scientific programs more portable.

Packed decimal was instituted for an entirely different reason. When a decimal number is converted into binary and then back to decimal again, there can be a slight rounding error. Consider as an example, 0.10, in decimal this is a simple rational number, 1/10, but in binary this number has an infinite expansion: 0.00011001100110011… Since there is only a finite amount of storage space, the infinite expansion is truncated, but when you convert from binary back to decimal, you might have a rounding error. So some programs, especially ones dealing with financial data use 4 bits to store each decimal place, or packed decimal.

Another distinction is the permitted length of an instruction. Most load-store architectures have fixed bit-length instructions, while register-memory ISAs often have variable length instructions.

Variable instruction length is often made out to be a disadvantage, but this is not necessarily true. Variable length instructions allow for more compact code, since commonly used instructions could be represented with only a couple of bits instead of several bytes. This means that the instruction caches seem larger, because they can hold more code. Variable length instructions also sometimes allow for prefixes and suffixes to be added to an instruction, which not only makes assembly programming easier, but it also lets the MPU transmit more information per instruction versus fixed length instructions.

However, variable length instructions definitely make decoding the instructions into electrical signals more complicated, which then requires more hardware to do the decoding. Ultimately, the choice of fixed or variable length instructions depends on the goal of the MPU. Once, once that is known, then it should become apparent whether fixed instructions should be used or not.

The architect must decide how many bits of branch displacement to support. That is, how far a typical branch can move the PC in the instruction stream. Most modern architectures support between 14 and 25 bits of branch displacement.

Lastly, an ISA can support many nifty features such as predication. Predication is the use of a bit in each instruction to indicate whether it can update the state of the machine, by writing to a register. If the ‘predicate bit’ is true (1), then it can modify state, if it reads false (0) then it cannot. Consider the following situation:

	if (y < x), then k = k + x
		else k = k – y

A non-predicated machine would have to choose between the two alternative branches (what does k equal?). This could result in the MPU waiting to finish evaluating the statement (y < x), or the MPU might simply guess that (y < x) is true and then change k, but later find out that y is actually greater than x (thus wasting time). A predicated MPU would compute what k would be in both situations and then simultaneous check if y < x, then set the predicate bits accordingly. This allows the processor to skip around this set of instructions without the risk of choosing the wrong branch. One drawback to this approach is that in doing so, the processor is ‘wasting’ resources, since one of the calculations is going to be discarded. There is another weaker form of predication, known as partial predication, where certain instructions, typically loads, can be predicated. These are then called conditional instructions. This is a more widely supported feature, because it is easier to add conditional instructions to an existing ISA than to try to and graft on full predication.

Here is a recap of the major differences in an Instructions Set:

  • Scalar or vector operations, or both
  • Two operand or three operand format
  • Operational model for operands
  • Addressing modes
  • Addressable memory
  • Endian-ness
  • Data formats supported
  • Fixed vs. Variable Length Instructions
  • Branch Displacement
  • Predication and other features

In the second part of this introductory sequence on computer architecture, software and hardware approaches to increasing parallelism will be discussed and explained.

References

[1] Dulong C., Krishnaiyer R., Kulkarni D., Lavery D., Lei W., Ng J., Sehr D., “An Overview of the Intel IA-64 Compiler”, in Intel Technology Journal, Q4 1999.

[2] IA-64 Application Developer’s Architecture Guide, www.intel.com, 2002.

[3] Hennessy J., Patterson D., “Computer Architecture: A Quantitative Approach”, Morgan Kaufman, 2002.


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