ARM’s Race to Embedded World Domination

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Conclusion

The ARM processor is a rarity – a non-American microprocessor instruction set architecture that has seen widespread commercial success. Nearly every major semiconductor manufacturer in the world has licensed at least one version of the ARM ISA from Advanced RISC machines Ltd. It is currently enjoying a huge wave in growth from design wins in cell phones, hand-held computers, and various embedded control applications, and is the highest volume 32-bit processor, RISC or CISC, on the planet. Like x86, ARM has adjusted to gradual evolution in its end use applications through judicious extension of the ISA.

Imitation is the sincerest form of flattery, and ARM has been honored by imitators seeking either to copy its philosophy (Motorola’s M*core) or direct functionality (picoTurbo Inc.). In part, ARM is successful because it doesn’t really directly compete against the performance and power points of superscalar MIPS and PowerPC processors targeted for the very high end of the embedded control market. But another important factor is the novel design extensions and features used to address specific market requirements. These include Thumb for improved code density, and now Jazelle for enhanced Java application performance. With widespread industry support and continued design innovation, there is ample reason to think ARM will continue to consolidate its unit shipment dominance in the 32-bit microprocessor market for years to come.

Footnotes

[1] Clarke, P., ‘ARM RISC leads the 32-bit Embedded Market’, Electronic Engineering Times, February 14, 2000.

[2] Smith, K., ‘Acorn goes to Market with RISC Microprocessor’, Electronics, August 5, 1985, p.14.

[3] Pountain, D., ‘The Archimedes A310’, Byte, October 1987, p.125.

[4] Cates, R., ‘Processor Architecture Considerations for Embedded Control Applications’, IEEE Micro, June 1988, p. 28.

[5] Turley, J., ‘Thumb Squeezes ARM Code Size’, Microprocessor Report, Vol. 9, No. 4, March 27, 1995, p. 1.

[6] Montanaro, J., ‘A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor’, JSSC, Vol. 31, No. 11, November 1996, p. 1703.

[7] Cataldo, A., ‘Intel Gives Muscle to StrongARM Processor’, Electronic Engineering Times, November 30, 1998.

[8] Turley, J., ‘StrongARM Speed to Triple’, Microprocessor Report, Vol. 13, No. 6, May 10, 1999, p. 1.

[9] Rayfield, J.,’ARM ISA SIMD Media Extensions’, Proceedings of Microprocessor Forum 2000, Cahners MicroDesign Resources.

[10] Cummins, A.,’ARM Jazelle Architecture Enhancements for Java Acceleration’, Proceedings of Microprocessor Forum 2000, Cahners MicroDesign Resources.

[11] Lindholm, T. and Yellin, F.,’The Java Virtual Machine Specification’, Addison Wesley, 1997. ISBN 0-201-63452-X.


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