Willamette Performance Revealed

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Recently released benchmarks for the new Pentium 4 processor look disappointing – but is it really a slug or a sleeper? Paul DeMone takes a close look at the SPEC numbers to divine the processor’s potential.

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ARM’s Race to Embedded World Domination

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What is the number one selling 32-bit microprocessor? Probably not what you think. Paul DeMone looks at the very successful ARM processor in this months Silicon Insider.

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A Big Blue Shadow over Alpha, SPARC, and IA-64

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IBM unveils a powerful 64-bit processor that may put them in the front of the performance race. Paul dissects it in this months Silicon Insider.

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Willamette Update

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Paul investigates why Willamette has only an 8 KB L1 cache, and why he feels this is beneficial to performance.

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From Russia, With Skepticism

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In this installment of Silicon Insider, Paul takes a hard look at the hype surrounding the E2k processor design from Elbrus. Is it a paper tiger, or just paper mache’?

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AMD’s 64 Bit Gamble

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Many readers wondered why AMDs upcoming 64-bit offering was absent from the “Battle Looming in 64-bit Land” article last month. Paul answers with this installment dedicated to AMDs interesting K8.

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The Looming Battle in 64 Bit Land

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Who are the real players in the 64-bit processor arena? Which company is likely to dominate the 64-bit landscape? In this installment of Silicon Insider, Paul investigates these questions

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Apple’s Power Failure

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Once upon a time, Apple was king-of-the-hill. A recent marketing campaign seems to imply they are back in the race – but are they? Paul investigates Apple’s situation and renders his judgement

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What’s Up With Willamette? (Part 2)

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This is the second of a two-part series in which Paul DeMone dissects the upcoming Willamette processor from Intel. In this installment Paul looks at the trace cache and ALU in detail, and speculates on what the performance might be.

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What’s Up With Willamette? (Part 1)

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In this first of a two-part series, Paul DeMone takes a look at the development roots of Willamette and the basics of how its organization and operation differs from earlier P6 generation processors

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