The Battle in 64 bit Land Revisited

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Summary and Conclusion

The official release of the Itanium raises troubling questions about the suitability of EPIC as an architectural approach for general purpose computing. Although the first generation IA64 processor and compilers are still relatively immature and will take many more years for either to reach the level of refinement seen in the RISC world, the apparent failure of the highly touted new architectural features to ameliorate the significant performance penalty associated with in-order execution on integer workloads cannot be ignored.

The Itanium demonstrates good performance on floating point intensive benchmarks and is competitive with current RISC designs. This should come as no surprise considering that the VLIW machines from firms like Multiflow and Cydrome that inspired EPIC targeted technical computing applications [3]. FP intensive code tends to have much more structure and predictability in data and control flow than general purpose and integer intensive code, and so is a much better match to VLIW and EPIC. Although Intel would naturally want to focus on the scientific and technical computing markets because of IA64’s bias towards FP performance, for strategic business reasons it is targeting Sun Microsystems whose strength lies primarily in commercial computing.

Ironically IA64 appears to be at least as vulnerable to competition from x86 processors as high-end RISC designs. The intense competition between Intel and AMD in the x86 market has created generation after generation of 32 bit x86 processors that have excellent integer performance and increasingly potent FP processing capabilities. It is hard not to compare the top end model Itanium (800 MHz, 4 MB L3) with the recently announced 1.7 GHz Pentium 4. The Itanium is priced more than an order of magnitude higher than the P4 and dissipates nearly twice as much power, yet the P4 provides more than 150% of the Itanium’s integer performance and 80% of its floating point performance.

Thus, IA64 market acceptance may be hampered because it cannot match the sales volumes, and therefore cost effectiveness, of x86 processors. At the same time, Intel’s chip merchant business model precludes cross-subsidization from high margin system sales, a model open to very high-end processors like POWER4 and Alpha EV7/8. If those two horns of a dilemma exist in practice, it may leave Intel vulnerable to AMD’s x86-64 family as the capability for flat addressing beyond 4 GB becomes a significant issue in sub $10k systems.

References

[1] Tredennick, N. and Shimamoto, B., “Mercy, Mercy, Merced”, Microprocessor Report, Vol. 13, No. 12, September 13, 1999, pp. 20-22.

[2] Advance Program, 2001 IEEE International Solid-State Circuits Conference, p. 35.

[3] Colwell, R. et al, “A VLIW Architecture for a Trace Scheduling Compiler”, IEEE Transactions on Computers, Vol. 37, No. 8, August 1988.


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