The Battle in 64 bit Land: Merchant Chips on the Rise

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Looking Ahead

Progress seldom slows in the semiconductor industry, and the high end 64 bit MPU segment is no exception. A list of new processors and new speed grades of existing processors that will likely be released later this year is shown in Table 1, along with estimates for their expected execution speed and throughput performance. IBM is expected to deliver both a higher frequency version of its existing POWER4+ device as well as introduce its new POWER5 in 130nm. Intel will counter with the Madison 9M, an update of the 130nm Itanium 2 Madison device with a 50% more capacious L3 cache and moderately higher clock rate. The Madison 9M reportedly supports significantly faster system bus operation than existing I2s, but delays in chipset support will push the release of this feature into next year. In addition, higher frequency versions of the Alpha EV7, Opteron, SPARC64 V, and US-IV are expected to ship.

Processor

Clock Rate

(GHz)

Estimated Execution Speed

(SPECbase2k)

Estimated Device Throughput

(SPECbase_rate2k)

  

int

fp

int

fp

Alpha EV7z

1.3

900

1250

10

15

Madison 9M

1.7

1600

2400

18

28

Opteron

2.4

1500

1600

18

19

POWER4+

1.9

1200

1750

27

36

POWER5

1.6

1100

1600

30

40

SPARC64 V

1.8

1000

1400

12

14

US-IV

1.5

750

1250

15

14


Table 1 – Imminent 64 bit Microprocessors

Things really get interesting in 2005, when the use of 90nm processing spreads to high end, server oriented processors. The resulting increase in transistor density will generally be used to shrink die size, cost, and power consumption. A notable exception to that trend will be a new IPF MPU known as Montecito. It will incorporate two instances of a third generation IA-64 core that introduces multi-threading capabilities, advanced dynamic power management, and replaces the 256 KB unified L2 cache of Madison with separate 256 KB L2 data cache and 512 KB L2 instruction cache. Each CPU core will have its own 12 MB unified L3 cache. This huge scale of resource integration ostensibly pushes Montecito’s die size to about 600 mm2, about as large a chip as is physically possible with current lithographic tools, despite 90 nm processing.

In sharp contrast, AMD will stick with the 1 MB L2 cache size of its 130 nm Opteron and ride the 90 nm shrink to a highly economical 114 mm2 die size. If AMD decides to join the CMP club, as is widely expected, it could produce a dual CPU Opteron in 90 nm with a separate 1 MB L2 cache per CPU that would be only a little larger than the existing 130nm device. Opteron will not be the only 90nm 64 bit x86 server processor next year. Intel will likely deliver Potomac, a Xeon MP family device based on the new, massively pipelined Prescott/Nocona core. A question mark hanging over Potomac is the extent to which Intel can resolve existing power consumption issues. The initial desktop version of this core has a thermal design power (TDP) of 103 W at 3.2GHz, with 64 bit capabilities disabled. The higher leakage current power and instruction throughput that would accompany the integration of a large L3 cache makes it hard to see how Potomac could scale in frequency relative to existing Xeon devices concomitant to its 50% longer pipeline and 90nm processing. The power consumption issue becomes even more problematic for a CMP based device using this core.

Next year HP will likely ship the final member of its PA-RISC processor family, the PA-8900. It will probably be a minimal effort shrink of the PA-8800 to 90nm, produced mainly to fill out a historical road map long promised to HP customers. Fujitsu plans to introduce a 90nm, dual CPU version of its existing SPARC64 V design. Designated SPARC64 VI, it will sport a 6 MB integrated L2 cache shared between the two CPU cores. The only serious challenger to Montecito for the high end server market next year will come from IBM in the form of a 90nm shrink of its upcoming POWER5 design. If it follows the pattern set by POWER4, it will be called the POWER5+ and will differ in design little from POWER5 beyond a possible increase in L2 cache capacity.


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