Tomorrow’s 64 bit Competitors
Estimates of physical and performance related characteristics for the processors described are provided in Table 2; these estimates were derived from current MPU characteristics and disclosed improvements. The effects of improvements in compiler technology or platform support (chipset, FSB speed, memory etc.) over the next 12 to 18 months were not included in the performance estimates.
|
Estimated: |
Montecito |
Opteron |
Opteron (CMP) |
PA-8900 |
Potomac Xeon |
POWER5+ |
SPARC64 VI |
|
Die Size (mm2) |
600 |
114 |
215 |
200 |
185 |
230 |
388 |
|
CPUs |
2 |
1 |
2 |
2 |
1 |
2 |
2 |
|
Transistors (millions) |
1650 |
106 |
205 |
317 |
380 |
350 |
690 |
|
L1 cache (I/D, KB) |
16/16 |
64/64 |
64/64 |
768/768 |
12*/16 |
64/32 |
128/128 |
|
L2 cache (MB) |
0. 5/0. 25 |
1 |
2 x 1 |
external |
1 |
2. 25 |
6 |
|
L3 cache (MB) |
2 x 12 |
– |
– |
– |
4 |
external |
– |
|
Clock Speed (GHz) |
2. 5 |
3. 2 |
2. 8 |
1. 2 |
4. 0 |
2. 5 |
2. 4 |
|
TDP power (W) |
110 |
70 |
110 |
60 |
120 |
130 |
100 |
|
SPECint_base2k |
2300 |
1900 |
1700 |
900 |
1900 |
1600 |
1250 |
|
SPECfp_base2k |
3500 |
2000 |
1800 |
950 |
1900 |
2300 |
1700 |
|
SPECint_base_rate2k |
62 |
23 |
38 |
21 |
22 |
45 |
27 |
|
SPECfp_base_rate2k |
87 |
23 |
36 |
20 |
20 |
58 |
28 |
The estimated relative size and conceptual floorplans of several of 90nm MPUs expected to ship by mid to late next year are shown below in Figure 2, along with some current and near term 130nm server processors.
Figure 2 – Relative Size of 130 and 90nm Server MPUs
When comparing the microprocessor floorplans in Figure 2, keep in mind that the green regions (cache data/tag arrays) have a high degree of protection from point defects by the incorporation of redundant circuit elements that can be used to repair affected structures to full functionality in most cases. In contrast, a point defect in a critical region (shown in Figure 2 as gray or blue) is almost always fatal. Multiprocessor designs also have a degree of redundancy in the sense that a device found to have a defective CPU may be recovered and sold as a single CPU variant at the vendor’s discretion.
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