The Battle in 64 bit Land: Merchant Chips on the Rise

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Tug of War: AMD, Intel, and 64 bit x86

The 32 bit x86 instruction set architecture has long dominated the market for personal computers and over the past five years has increasingly defined the low end of the server market. Although x86 servers are in many cases glorified PCs, what they lack in gravitas is made up for in volume. Of all the computers that shipped in 2003 with the designation of server, about nine out of every ten were powered by one or more x86 processors, a quantitative lead sufficient to capture about 44% of sales in a $50B market in 2003 according to market research firm IDC.

One of the more important distinctions between x86 based systems and the proprietary RISC and CISC processors powering the high end systems that still capture the majority of server sales revenue is that the latter have a 64 bit instruction set architecture that allows flat addressing of memory spaces beyond 4GB in size. Intel was happy to preserve the distinction between low end 32 bit x86 servers (a market it basically invented and owned) and high end non-x86 servers as long as it could grab a major piece of the high end action for its own 64 bit Itanium processor family (IPF). But AMD upset the apple cart by removing the 32 bit versus 64 bit distinction between x86 and non-x86 architectures when it introduced the Opteron processor family about a year ago.

So Intel was faced with a dilemma. Its IPF family was finally making good progress in the very high end of the server market but its cost structure was more expensive than Xeon and the limited amount of software available for IPF hinders its uptake in many markets. Like the proprietary RISC MPU families it is intended to replace, IPF’s disadvantages become more pronounced as one moves downscale to market segments where x86 and non-x86 based systems overlap – workstations and low end servers. Intel’s Xeon family dominates the x86 server and workstation market but at the high end of that market – technical workstations and four processor servers, the 4 GB flat addressing limit is increasingly making itself felt. Serendipitously or not, AMD launched the Opteron into this weak middle ground with maximum effect.

Intel responded with a two prong strategy. It recognized that it had to bring down the cost structure for IPF products to keep from artificially constraining IPF to the high end of the server market. To this end, Intel has announced plans to converge the system interfaces and possibly package pinouts of future IPF and Xeon processors to a common standard to allow the two server MPU families to share hardware development costs for chipsets and motherboards. The second prong of Intel’s strategy is to introduce AMD64 compatible x86 processors of its own in the near future to take away 64 bitness as marketing leverage against Xeon based systems. Nevertheless it is clear that Intel views IPF as its long term 64 bit solution for servers, as it claims that by 2007 Itanium processors will deliver twice the performance at the same cost as their socket compatible 64 bit Xeon brethren.

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