IBM’s Power Trip
For a technology powerhouse that pioneered the technology of the modern RISC era a decade before anyone else, IBM’s record of commercial success in RISC processors has been a mixed bag. In 1974 John Cocke and fellow researchers at IBM’s Thomas J. Watson Research Center began to research the design of a central control processor for an all digital telephone exchange. This research eventually evolved into the what was known as the 801 project, which laid down the foundations for the processor design and compiler technology for the RISC revolution a decade later.
In the seventies IBM was a colossal force in the computer industry and a new method of designing CPUs that could make $60,000 worth of ECL chips and circuit boards equal or surpass the performance of multi-million dollar mainframe CPUs was not exactly welcome. IBM essentially sat on what it learned from the 801 project for more than a decade until the RISC message was spread far and wide through the efforts of bay area university professors David Patterson and John Hennessy. When IBM did decide to enter the RISC market it was with a product, the PC/RT, which was so pathetically underpowered that some industry observers thought IBM was trying to sabotage the RISC movement.
IBM’s second effort, the RS/6000, was far more serious, a massive, multi-chip implementation (RIOS) of a RISC architecture called POWER. Although the RS/6000 never challenged other RISC or even CISC processors for the clock frequency crown, its ample low latency execution resources, custom cache chips, and huge memory bandwidth allowed it to turn very respectable performance levels, particularly on floating point applications. The 1.0 um CMOS Power CPU chipset was eventually shrunk to 0.70 um. A subsequent shrink and tweak became known as the Power 2 while single chip versions of POWER, called RSC (RIOS Single Chip) and RSC2, were also created. More recently IBM has delivered full-blown single chip implementation of POWER called Power3 (0.25 um CMOS) and Power3-II (0.22 um CMOS, copper).
In late 1991 Apple Computer Inc. was searching for a RISC processor to replace the 68K CISC processor line in its Macintosh desktop computers. Early experimental Macintoshes were based on the Motorola 88K RISC processor line. For some reason Apple decided the 88K would never cut it and convinced Motorola and IBM to jointly create a new RISC architecture called PowerPC that was basically POWER rationalized for desktop computing. The initial product, the PowerPC 601 was essentially an RSC2 modified to support both POWER and PowerPC ISAs with an 88K bus interface grafted on (Apple wanted to protect its early investment in chipsets). A joint CPU design center called Somerset was set up by IBM and Motorola, and a three product roadmap was defined – the 603, the 604, and the 620. Only the PowerPC 620 was a full 64-bit version of the PowerPC architecture. But the 620 was years late coming to market and in the end only shipped in tiny quantities to presumably fulfill certain contractual obligations. The first widely shipping 64-bit version of the PowerPC was the RS64; a design originally developed to provide a platform for the evolution of IBM AS/400 line of minicomputers. The RS64-II, or Northstar, is a continuation of this line into 0.25 um CMOS technology). These processors turn in mediocre performances for technical and scientific computing applications, but were designed mainly for commercial applications. There, they are competitive with x86 Xeon and other RISC on the strength of their short, low latency pipeline and wide, high bandwidth system interface.
All in all, IBM’s record in high-end microprocessors has been mediocre, given the enormous technical breadth and width of this once formidable corporation. This is especially surprising considering its strength in inventing and exploiting breakthroughs in new semiconductor technologies that even chip giant Intel cannot begin to match. IBM seems to have realized its underachiever status and has mobilized forces from all corners of its kingdom for a tremendous technological push directed at preventing total IA-64 domination in the 64-bit processor market. The spearhead of this offensive is the packaging wonder known as POWER4. This is a massive processor manufactured in IBM’s CMOS8S2 0.18 um copper interconnect SOI process. This device incorporates two 5-issue wide superscalar RISC cores that implement the 64 bit version of the PowerPC ISA. These two processors, operating at clock rates in excess of 1 GHz, are teamed with a large, shared on-chip L2 cache, a controller for an external L3 cache, and three sets of high bandwidth interprocessor communication links. This arrangement allows four POWER4 dice to be incorporated into a large multi-chip module (MCM), with each device fully connected to its three neighbors. The MCM is mounted within a thermal conduction module (TCM) of the type IBM perfected long ago for its mainframe CPUs. A single POWER4 TCM, which is about 4.5 inches on a side, incorporates all the elements of a fully connected 8-way multiprocessor system, with tremendous amount of potential interprocessor, memory, and I/O bandwidth.
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