We previously theorized that Intel’s TSX extensions in Haswell use the caches to provide transactional memory semantics. This article describes an alternative approach based on minimal changes to the CPU core, contrasts the advantages of the two techniques and discusses the expected implementation in Haswell.
Haswell Transactional Memory Alternatives
August 21, 2012 by
Read More (3 pages)Discuss (30 comments)
ARM Goes 64-bit
August 14, 2012 by
The new ARMv8 architecture is classically British; a clean and elegant 64-bit instruction set, with compatibility for 32-bit software. The 64-bit mode eliminates many complicated and awkward features and will foster a larger and more diverse ARM ecosystem with new licensees and applications.
HP Wins Oracle Lawsuit
August 1, 2012 by
HP has won its lawsuit against Oracle over the Itanium platform. Good news for HP, customers and the industry, as Oracle is required to update and support existing Itanium software as long as HP continues to sell servers.
Computational Efficiency for CPUs and GPUs in 2012
July 25, 2012 by
New compute efficiency data shows GPUs with a clear edge over CPUs, but the gap is narrowing as CPUs adopt wide vectors (e.g. AVX). Surprisingly, a throughput CPU is the most energy efficient processor, offering hope for future architectures. Our data also shows some advantages of AMD’s Bulldozer, and the overhead associated with highly scalable server CPUs.
Behind RWT 3.0
July 23, 2012 by
Our previous website was a fully custom Cold Fusion application that incorporated both a primitive Content Management System (CMS) and a very active threaded forum. As with most Cold Fusion applications, the back-end was Microsoft SQL Server. One of the biggest challenges with our old website was adapting to the rapid pace of change on […]
Welcome to Real World Tech 3.0
July 23, 2012 by
We’d like to welcome everyone to the latest and best incarnation of Real World Tech (RWT). RWT started 16 years ago and has grown to become one of the leading venues for deep technical analysis of the computer and semiconductor industries. Over the years, the internet has evolved considerably and our new website design is […]
Sandy Bridge-EP Review
April 3, 2012 by
In our Sandy Bridge-EP and Romley platform review, we look at the performance and power efficiency gains for Intel’s latest server microprocessor on industry standard benchmarks including SPECcpu2006 and SPECpower_ssj2008. The results are impressive, Sandy Bridge-EP is clearly the best x86 server processor on the market, and Romley will be the platform of choice for the next 2 years.
Impressions of Kepler
March 22, 2012 by
Our first look at Kepler focuses on architectural changes to the shader core that emphasize graphics performance and the enhanced power management. Based on our analysis of Nvidia’s 28nm GPU strategy, we project a new shader core for throughput computing products and discuss the expected features.
Sandy Bridge-EP Launches
March 6, 2012 by
Sandy Bridge-EP is the first major overhaul for Intel servers since 2009, and nearly ever aspect has been enhanced. The processor pairs 8 cores with a large last level cache, DDR3 memory controller, QPI 1.1, integrated PCI-E and power management. This article provides an overview of the major features, including new I/O optimization and power capping techniques and discusses the expected impact.
Analysis of Haswell’s Transactional Memory
February 15, 2012 by
Intel’s upcoming Haswell microprocessors include transactional memory and hardware lock elision that are exposed through the Transactional Synchronization Extensions or TSX. In this article, I discuss TSX and predict the implementation details of Haswell’s transactional memory and expected adoption across the industry, based on my previous experience.
