ISSCC 2008 Cell Processor Update

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Die Size Scaling Much Less than Linear

In the 45 nm CELL processor presentation, IBM was rightfully proud to boast that it was able to dramatically lower power consumption of the processor with minimal design resources – estimated at (low) ten’s of man-years of design effort spent in the successful port of a highly complex modern processor from one process technology to another process technology. The low amount of (re)design effort was no doubt the result of efficient application of effort by the team that contributed the ten’s of man-years of effort. But it is also fundamentally enabled by a highly automated design flow that started with the re-use of the basic floorplan and highly automated shrinks of the basic functional blocks. The cost of the design methodology and low power focus means that the die size scaling was far from linear.

Figure 2 – Area comparison of the CELL processor in 90, 65 and 45 nm processes – presented by IBM

Figure 2 illustrates the point that the 45-nm-CELL processor, was only scaled down to 49% of the 90-nm-CELL processor.

Figure 3 – Die photo of the 45 nm CELL processor – presented by IBM

Astute readers will note that the table in Figure 2 shows that the basic blocks (SPE, PPE) of the CELL processor scaled much better than the CELL processor as a whole. The fundamental issue is that in the desire to minimize design effort and maintain the basic floorplan, the scalability of the processor as a whole is constrained by the scalability of the least-scalable basic blocks. As to be expected, the least scalable basic blocks are the I/Os: Rambus FlexIO and XDRAM Interfaces. This is due to the nature of I/O interfaces that have specific connectivity requirements, not due to anything that can be blamed on Rambus.

Figure 3 illustrates the point that although the logic circuits in the SPE and PPE blocks can be scaled to a higher degree than the I/O blocks, the 45 nm CELL processor is constrained in the y-dimension by the height of the I/O blocks – forcing the chip designers to leave unused spaces on the periphery of the 45 nm CELL processor.

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