Multiple Clock Domains and Clock Gating Control
Figure 6 – Circuit Depths in the SPE
At ISSCC 2005, IBM revealed that the CELL processor is designed to operate at high clock frequencies, and the per-stage circuit delay is limited to 11 FO4, including latch delays. Furthermore, IBM indicated that with a circuit delay depth of 11 FO4, oftentimes only 5–8 FO4 are left for inter-latch logic flow. At Cool Chips, IBM clarified this breakdown; the short circuit depth is only found in clock gating circuit paths, while normal circuit paths not used for clock gating have 8–9 FO4 for logic flow. Furthermore, IBM revealed that in fact two separate clocking domains exist on the CELL processor. The fast clock domain is limited to 11 FO4 per stage and the slow clock domain operates at 22 FO4 per stage. Figure 6 illustrates the circuit depths available in each clock domain.
Figure 7 – Clock Domain partitions in the SPE
Figure 7 shows the boundary of the fast 11 FO4 clock domain and the slow 22 FO4 clock domain. Figure 7 illustrates that while the core of the SPE operates in the fast 11 FO4 clock domain, the entire interface of the SPE operates at the slow 22 FO4 clock domain.
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