CELL Microprocessor III

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References

[1] J. Silberman et. al., “A 1.0- GHz Single-Issue 64-Bit PowerPC Integer Processor”, IEEE Journal of Solid-State Circuits, Vol 33, No.11, Nov 1998.

[2] P. Hofstee et. al., “A 1 GHz Single-Issue 64b PowerPC Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2000.

[3] N. Rohrer et. al. “PowerPC in 130nm and 90nm Technologies”, International Solid-State Circuits Conference Technical Digest, Feb. 2004.

[4] B. Flachs et. al. “A Streaming Processing Unit for A CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.

[5] D. Pham et. al. “The Design and Implementation of a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.

[6] J. Kuang et. al. “A Double-Precision Multiplier with Fine-Grained Clock-Gating Support for a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.

[7] S. Dhong et. al. “A 4.8 GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.

[8] K. Chang et. al. “Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.

[9] H. Hofstee, “Power Efficient Processor Architecture and the Cell processor”, Proceedings of the Eleventh International Symposium on High-Performance Computer Architecture (HPCA 11).

[10] D. Wang, “ISSCC 2005: The CELL Microprocessor”, http://www.realworldtech.com/page.cfm?ArticleID=RWT021005084318

[11] D. Wang, “Cell Microprocessor Revisited“, http://www.realworldtech.com/page.cfm?ArticleID=RWT022805234129

[12] K. Krewell, “Cell Moves Into the Limelight”, Microprocessor Reports, February 14, 2005.

[13] M. Suzuoki, “Cell Future: New Challenge in Micro-architecture and Compiler Design”, Proceedings of COOL chips VIII, April 2005.

[14] P. Hofstee, “All About the CELL Processor”, Proceedings of COOL chips VIII, April 2005.

[15] O. Takahasi, “The Power Conscious Design of the Synergistic Processor Element of a CELL Processor”, Proceedings of COOL chips VIII, April 2005.

[16] T. Asano et. al., “Low Power Design in 11 FO4 Embedded SRAM for the Synergistic Processor Element of a CELL Processor”, Proceedings of COOL chips VIII, April 2005.

[17] S. Maeda et. al., “A CELL Software Platform for Digital Media Applications”, Proceedings of COOL chips VIII, April 2005.

[18] Sony Playstation 3 Press Release http://www.us.playstation.com/Pressreleases.aspx?id=279

[19] Arnd Bergmann, “Spufs: The Cell Synergistic Processing Unit as a virtual file system. The Linux programming model for Cell”, http://www-128.ibm.com/developerworks/power/library/pa-cell/?ca=dgr-pow03SpufsCell

Copyright:

Copyright 2005 David T. Wang. All rights reserved. No portion of this article, in part or whole, may be reproduced, copied, transmitted, stored, downloaded, in any manner in any way, for any purpose whatsoever without the express written consent from the author.

Misc. Notes:

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About COOL Chips VIII proceedings: COOL Chips VIII conference proceedings can be obtained by contacting Mr Yutaka Uchida of COOL Chips. The cost of the proceedings is 8100 yen, and Mr Uchita can be reached at cool-1@ieice.org. Unfortunately, COOL Chips does not accept credit cards, so a wire transfer is likely the best option for payment.

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