ISSCC 2005: The CELL Microprocessor

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This is the first of two articles on the CELL microprocessor, the second contains several clarifications and elaborations on the capabilies of the XDR memory system and the multiprocessor capabilities of CELL. It can be found here.

The fundamental task of a processor is to manage the flow of data through its computational units. However in the past two decades, each successive generation of processors for personal computers has added more transistors dedicated to increasing the performance of spaghetti-like integer code. For example, it is well known that typical integer codes are branchy and that branch mispredict penalties are expensive; in an effort to minimize the impact of branch instructions, transistors were used to develop highly accurate branch predictors. Aside from branch predictors, sophisticated cache hierarchies with large tag arrays and predictive cache prefetch units attempt to hide the complexity of data movement from the software, and further increase the performance of single threaded applications. The pursuit of single threaded performance can be observed in recent years in the proposal of extraordinarily deeply pipelined processors designed primarily to increase the performance of single threaded applications, at the cost of higher power consumption and larger transistor budgets.

The fundamental idea of the CELL processor project is to reverse this trend and give up the pursuit of single threaded performance, in favor of allocating additional hardware resources to perform parallel computations. That is, minimal resources are devoted toward the execution of single threaded workloads, so that multiple DSP-like processing elements can be added to perform more parallelizable multimedia-type computations. In the examination of the first implementation of the CELL processor, the theme of the shift in focus from the pursuit of single threaded integer performance to the pursuit of multiply threaded, easily parallelizable multimedia-type performance is repeated throughout.

CELL Basics

The CELL processor is a collaboration between IBM, Sony and Toshiba. The CELL processor is expected by this consortium to provide computing power an order of magnitude above and beyond what is currently available to its competitors. The International Solid-State Circuits Conference (ISSCC) 2005 was chosen by the group as the location to describe the basic hardware architecture of the processor and announce the first incarnation of the CELL processor family.

Members of the CELL processor family share basic building blocks, and depending on the requirement of the application, specific versions of the CELL processor can be quickly configured and manufactured to meet that need. The basic building blocks shared by members of the CELL family of processor are the following:

  • The PowerPC Processing Element (PPE)
  • The Synergistic Processing Element (SPE)
  • The L2 Cache
  • The internal Element Interconnect Bus(EIB)
  • The shared Memory Interface Controller (MIC) and
  • The FlexIO interface

Each SPE is in essence a private system-on-chip (SoC), with the processing unit connected directly to 256KB of private Load Store (LS) memory. The PPE is a dual threaded (SMT) PowerPC processor connected to the SPE’s through the EIB. The PPE and SPE processing elements access system memory through the MIC, which is connected to two independent channels of Rambus XDR memory, providing 25 GB/s of memory bandwidth. The connection to I/O is done through the FlexIO interface, also provided by Rambus, providing 44.8 GB/s of raw outbound BW and 32 GB/s of raw inbound bandwidth for total I/O bandwidth of 76.8 GB/s. At ISSCC 2005, IBM announced that the first implementation of the CELL processor has been tested to operate at frequencies above 4 GHz. In the CELL processor, each SPE is capable of sustaining 4 FMADD operations per cycle. At an operating frequency of 4 GHz, the CELL processor is thus capable of achieving a peak throughput rate of 256 GFlops from the 8 SPE’s. Moreover, the PPE can contribute some amount of additional compute power with its own FP and VMX units.

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