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Summary
The CELL processor presents an intriguing alternative in its pursuit of performance. It seems to be a forgone conclusion that the CELL processor will be an enormously successful product, and that millions of CELL processors will be sold as the processors that power the next generation Sony Playstation. However, IBM has designed some features into the CELL processor that clearly reveals its ambition in seeking new applications for the CELL processor. At ISSCC 2005, much fanfare has been generated by the rating of 256 GFlops @ 4 GHz for the CELL processor. However, it is the little mentioned double precision capability and the yet undisclosed system level coherency mechanism that appear to be the most intriguing aspects that could enable the CELL processor to find success not just inside the Playstation, but outside of it as well.
References
[1] J. Silberman et. al., “A 1.0- GHz Single-Issue 64-Bit PowerPC Integer Processor”, IEEE Journal of Solid-State Circuits, Vol 33, No.11, Nov 1998.
[2] P. Hofstee et. al., “A 1 GHz Single-Issue 64b PowerPC Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2000.
[3] N. Rohrer et. al. “PowerPC in 130nm and 90nm Technologies”, International Solid-State Circuits Conference Technical Digest, Feb. 2004.
[4] B. Flachs et. al. “A Streaming Processing Unit for A CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.
[5] D. Pham et. al. “The Design and Implementation of a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.
[6] J. Kuang et. al. “A Double-Precision Multiplier with Fine-Grained Clock-Gating Support for a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.
[7] S. Dhong et. al. “A 4.8 GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.
[8] K. Chang et. al. “Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor”, International Solid-State Circuits Conference Technical Digest, Feb. 2005.
Copyright 2005 David T. Wang. All rights reserved. No portion of this article, in part or whole, may be reproduced, copied, transmitted, stored, downloaded, in any manner in anyway for any purpose whatsoever without the express written consent from the author.
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