Chip Multi-Processing: A Method to the Madness

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Future Directions

While the main focus of this article is to describe current and near-term CMP designs, it is worthy to mention some ways that CMP could evolve in the future. In terms of the evolution of CMP, one can envision higher levels of integration, in which more resources besides the cache and I/O interface are shared. AMD, for example, has discussed some possible hybrid approaches where certain front-end elements of a CPU can be shared between cores. This may come with a benefit to die size and potentially allow more cores to be integrated in a single piece of silicon, or possibly lower power in existing designs.

Another way to get a glimpse of the future is to look at current SMP designs and think how they would adapt to a single chip. In order to support the next generation of 4-way CMP, one possibility would be to use a SI-CMP architecture, but then have a crossbar switch connecting all the caches together. Alternatively, a ring interconnect could replace the crossbar and scale to many more cores.

Multiple approaches may also be combined, such as a pair of shared cache dual core chips integrated into a single shared package, resulting in 4 total cores. For example, a pair of Yonah chips (each with two cores) is small enough to share a package to create a 4P module. These are just a few of the possibilities out there and it will be interesting to look for when it comes to future designs.


The design trade-offs for CMP microprocessors are a relatively undocumented and are an under-discussed aspect of computer architecture. In many respects, this is simply a reflection of the fact that scalable multiprocessor systems are incredibly complex. However, as CMP designs become more common, it is essential to understand the distinctions between different approaches.

The crucial theme here is that architects will have to compromise between performance and design complexity with the level of integration they decide to implement. In many cases, the schedule is of such high importance that a longer design time is unacceptable, no matter the performance benefit. Conversely, architects planning out 3-7 years have the luxury of choosing the course of highest integration. Higher performance may generally win out, but there are many variables to consider, such as price, time to market, die size and yields. Ultimately, it is up to architects to make the decisions, but hopefully, this guide will help you to understand their motivation.

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