The Stuff Dreams Are Made Of [Part 1]

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Transistor Yin and Yang

There are two basic types of field effect transistor (FET) that can be constructed, the n-channel FET (NFET) and the p-channel FET (PFET). The physical structure of the NFET and PFET are shown in Figure 1.


Figure 1 Physical Structure of the NFET and PFET

The NFET starts with an underlying body or substrate of p-type silicon. Two side by side regions in the top of the substrate are changed to n-type silicon by introducing (or implanting) a higher concentration of n-type dopant atoms than the concentration of p-type dopant atoms in the substrate. This is also known as an n+ implant, the “+” indicates a relatively high doping density. The two n+ regions are known as the source and drain. The designation is essentially arbitrary because a FET is electrically symmetrical and will function identically if source and drain are swapped. Because the source and drain regions are separated by p-doped silicon (which is generally kept at the lowest voltage potential on the chip) no current can flow between them. A field effect transistor is formed by depositing a polycrystalline silicon (also known as polysilicon or poly) structure called the gate over the substrate and between the source and drain regions. The gate is electrically isolated from the source, drain, and substrate region by an extremely thin layer of insulator called the gate dielectric.

The gate dielectric is typically silicon dioxide (SiO2) and in the early days of the semiconductor industry the gate was composed of a metal like aluminum rather than polysilicon. This metal, oxide, semiconductor sandwich used historically to form FETs gave this technology the name MOS and why FETs are sometimes called MOSFETs. In modern MOS processes the polysilicon gate is actually formed before the source and drain regions are implanted and helps to precisely define the inner, opposing edges of the n+ implant. This technique is called self aligned gate and allows much faster transistor operation due to virtual elimination of the overlap between the gate and source and drain regions that creates parasitic capacitance. (The minute amount of overlap shown in Figure 1 is due to the fact that the dopant atoms in the source and drain regions tend to diffuse laterally a little bit during manufacturing).

The NFET operates when the voltage of the gate is raised relative to that of the source or drain region. The electric potential on the gate generates an electric field that tends to pull electrons from the source or drain region into the substrate immediately underneath the gate to balance the positive charge on the gate. If the gate voltage reaches a high enough level, the threshold voltage, the concentration of electrons in the substrate under the gate close to the dielectric (the channel region) will exceed the hole density in the p-type substrate. That charge carrier ratio inversion creates an effectively n-type region in the channel that allows current to flow from source to drain or vice versa. The higher the amount by which the voltage on the gate exceeds the threshold voltage, the greater the excess concentration of electrons in the channel and more current can flow.

The PFET is a mirror image (or complement) of the NFET. It starts with an n-type substrate (or well i.e. a substrate within a substrate) into which p-type source and drain regions are implanted on either side of a gate structure. The ‘n’ substrate is generally tied to the highest voltage potential on the chip. The PFET operates when the voltage of the gate is lowered relative to that of the source or drain region. When the gate voltage is lowered below a specific level, again called the threshold voltage, the concentration of holes induced in the channel region under the gate exceeds the background electron density in the n-substrate and the channel region is inverted to effectively p-type doping, which allows current to flow between source and drain and vice versa. The more the gate voltage is lowered below the threshold voltage the higher the excess hole concentration in the channel and more current can flow.


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