Paying the Ultimate Complement
The rise of the monolithic microprocessor and high density semiconductor memory began in the 1970’s with the 4 bit microprocessor and the 1 Kb DRAM, both introduced by Intel and both based on PMOS technology. PMOS devices incorporate digital logic composed entirely of p-channel field effect transistors (PFETs). This was soon superseded by faster NMOS technology, which uses n-channel field effect transistors (NFETs) to form logic circuits. CMOS has both NFETs and PFETs (its name comes from the fact that it has the two complementary types of FETs) and went mainstream in the early 1980’s with early 32-bit microprocessors like the MC68020 and i80386, as well as 256Kb DRAMs. Although CMOS integrated circuits require more processing steps to manufacture than PMOS or NMOS based devices and have slightly lower logic density, its desirable qualities far outweigh those considerations. CMOS has dominated the semiconductor industry for the past two decades, and this domination will continue for years to come as there is no credible successor in sight that can match all its strengths as well as exceed it in either performance or cost effectiveness.
The reason why having both NFETs and PFETs available is such a tremendous advantage arises from the process of constructing digital logic, the mathematical building block of computers and modern telecommunications. As most people know, digital logic relies on two discrete signal states commonly represented as the binary digits 0 and 1. These are typically represented in circuitry by low and high voltage levels respectively. When only one type of transistor is available, like NFETs in an NMOS process, logic circuitry is often constructed using a weak transistor that is always on and one or more strong transistors that are switched on and off. In NMOS the weak transistor is used to generate a high output voltage level or 1 when the strong transistors are turned off. When a strong transistor turns on it overwhelms the weak transistor and forces the output voltage low, which represents a 0. The process by which NMOS logic circuitry generates a 0 output consumes a steady stream of DC current, which is turned directly into heat. In addition, because of the disparity in strength between the weak and strong transistors, a NMOS logic circuit has a pronounced asymmetry in switching speed. It may take four times longer, or more, for a circuit output to switch from a 0 to 1 than from a 1 to a 0, yet one more headache for design engineers.
With a CMOS process, logic circuits can be constructed with both NFETs and PFETs in such a way that transistors never fight against each other except momentarily when switching states, and thus consume virtually no DC current when left quiescent in either output state. A side effect of this property is the ability to control power consumption over a tremendous range by adjusting the amount of switching activity per unit time as the application permits. This can be done by reducing an MPU’s clock frequency, for example, or automatically disabling the clock to unused function units like a FPU. This attribute is a tremendous advantage for CMOS in being able to exploit Moore’s Law. One of the last high-performance microprocessors constructed using NMOS logic was an early PA-RISC processor designed and manufactured by HP. This 1.5 um MPU used 71k transistors and consumed 10 Watts at 15 MHz. The next generation PA-RISC chip was implemented in 1.0 um CMOS. It contained 196k transistors, ran at 32 MHz and consumed 7.5 Watts. The amazing progress made in the microprocessor field over the last twenty years would have been a lot less impressive if CMOS didn’t exist.
In addition to much lower effective power consumption, CMOS logic circuits can be balanced to have nearly symmetrical switching speeds. That is, the output can change from a 0 to a 1 as fast as from a 1 to a 0. In very rare and specific cases it may be desirable to build logic using an NMOS style methodology with constant current draw. The beauty of CMOS is that it is flexible enough to accommodate a wide variety of circuit design styles, including what is called pseudo-NMOS that can accommodate such needs. Another advantage of CMOS is that its logic circuits are very resistant to electrical design errors, like an error in transistor sizing. Using a wrong sized transistor in an NMOS circuit can render it completely non-functional, while a conventional CMOS circuit will still operate robustly, although perhaps at somewhat reduced speed. This makes it much simpler to automate the design of chips, or portions thereof, where the ultimate in performance is not required.
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