Gates within Gates
Because CMOS logic circuits do not depend on detailed transistor electrical performance it is possible to understand their function using a simplified switch model for NFET and PFET transistors. The schematic symbol and simplified switch model for the NFET and PFET are shown in Figure 2 (the connection to the transistor substrate or body is sometimes denoted as a fourth terminal, B, on the FET symbol but for purely digital design it is often ignored through use of a 3 terminal symbol because it is invariably tied off to the appropriate power supply).
Figure 2. Symbol and Conceptual Switch Model of the NFET and PFET
In conceptual terms, the NFET and PFET both act like switches that can be closed (turned on) and thus conduct electrical current between the source and drain terminals. These switches turn on and off under control of the voltage applied to the gate terminal. The NFET model is that of a switch that is open when a low voltage (0) is applied to the gate and on when the gate is raised to a high voltage level (1). The PFET operates in a complementary fashion – it conducts current when the gate voltage is low (0) and turns off when the gate voltage is raised to a high level (1).
The simplest CMOS logic gate (the word gate is confusingly used to denote both the controlling structure in a FET and as a general term for a basic logic circuit, e.g. an AND gate) is called the inverter and its symbol, schematic and operation are shown in Figure 3.
Figure 3 Basic CMOS Inverter
The inverter has terminals, an input and an output and it simply converts a logic 0 to a logic 1 and a logic 1 to a logic 0. Besides the obvious role as a means to flip the sense of a logic value the inverter is also used to restore and/or amplify weak or noisy logic signals. The basic CMOS inverter is composed of one NFET and one PFET. The input of the inverter connects to the gate of both transistors. The source of the NFET is tied to Vss (the low voltage power supply, equivalent to a logic 0) while its drain connects to the inverter output. The drain of the PFET is connected to Vdd (the high voltage power supply, equivalent to a logic 1) while its source connects to the inverter output.
Since the inverter input controls both the NFET and PFET simultaneously, one transistor is always on while the other is always off. If the input is a logic 0 then the PFET is turned on while the NFET is turned off. The PFET will source current from the Vdd supply to the output until its voltage level is raised to that of Vdd, which is a logic 1. If the input is a logic 1 then the PFET is turned off while the NFET is turned on. The NFET will sink current from the output to the Vss supply until the output voltage level falls to that of Vss, which is a logic 0.
The inverter is an essential logic element but by itself cannot do anything particularly useful. For that you need logic gates with two or more inputs. The simplest multiple input logic gates in CMOS are the two input negative-AND (NAND) gate and the two input negative-OR (NOR) gate. The NAND gate outputs a 0 when all its inputs are 1, otherwise its output is 1. The NOR gate outputs 0 when any of its inputs are 1, otherwise its output is 1. All possible Boolean logic function can be built using just NAND or NOR gates. Thus theoretically speaking it is possible to build an entire CPU entirely out of NAND or NOR gates although in practice this is often far from optimal. The symbol, schematic, and truth table for the basic CMOS two input NAND and NOR gates are shown in Figure 4.
Figure 4 Basic CMOS two input NAND and NOR gates
The NAND and NOR gates are specific examples of the general form of a static CMOS logic gate. That is, the output is connected to Vdd through a network of PFETs and to Vss through a complementary network of NFETs. In this context, complementary networks of PFETs and NFETs means that for every combination of inputs the output is always connected either just to Vdd through turned on PFET(s) or just to Vss through turned on NFET(s). A properly designed CMOS logic gate will never float the output (i.e. leave it not connected electrically to either Vdd or Vss) or create a short circuit path for current to flow from Vdd to Vss.
The two input NAND gate has two NFETs and two PFETs. The NFETs are in series while the PFETs are connected in parallel. That means that for the output to be low (0) both NFETs must be turned on (i.e. both inputs high or 1). The topology of the NOR gate is the same as that of the NAND gate but turned upside down. The output of the NOR gate is only high or 1 when both PFETs are turned on (i.e. both inputs are low or 0). Static CMOS NAND and NOR gates can be extended to any arbitrary number of inputs by adding more series and parallel FETs to the circuit, although in practice when NAND or NOR functions with fan-in (i.e. the number of inputs) greater than 3 or 4 are required these are usually implemented in a different fashion for performance reasons.
In the second installment of this two part article I will describe the operation of field effect tranistors in more detail using the example of a state of the art 0.13 um process and examine how FET characteristics affect logic performance. This will lead into an examination of the more advanced logic circuit design techniques used in modern MPUs to achieve the highest possible clock frequencies and performance.
 Maly, W., “Atlas of IC Technologies”, Benjamin/Cummings Publishing Company Inc., ISBN 0-8053-8650-7, 1987.
 Weste, N. and Eshraghian, K., “Principles of CMOS VLSI Design, A Systems Perspective”, Addison-Wesley Publishing Co, ISBN 0-201-08222-5, 1985.
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