This is the second installment of a two-part article that examines CMOS, the nearly perfect technology for implementing the digital logic that powers much of our modern age. In the first part the n-type and p-type field effect transistor were introduced along with how these are combined to form basic logic gates. In this second part I’ll examine performance issues and the specialized methods microprocessor engineers use to reach today’s GHz clock rates.
Size Matters
The first issue to address is the role that a field effect transistor, or FET’s, physical size plays in its operation. The circuit designer has control over transistor sizing in two dimensions, length and width as shown in Figure 1. The electrical drive strength of a FET, to a good approximation, is proportional to its width W divided by its length L. However, a FET can have several different lengths attributed to it and this sometimes causes confusion when describing CMOS processes.
Figure 1 Transistor Sizing
The drawn transistor length, or Ldrawn, is the width of the gate material specified by the layout engineer and captured in a computerized physical data base (this is shown in Figure 1 as the width of the shape in the gate mask, although this isn’t strictly accurate as sometimes the feature size on the mask is often biased, i.e. lengthened or shortened by software during mask creation to account for changes in the process over time). A CMOS process is typically described by the minimum drawn transistor length it supports, e.g. a 0.13 um process. The actual transistor length or Lactual, is the actual physical width of the gate material after the etching process used to shape it during manufacturing and is typically somewhat smaller than Ldrawn.
In a self-aligned CMOS process the source and drain regions are doped after the gate dielectric and gate conductor are laid down and shaped. During this so-called implant step, and high temperature manufacturing steps later on, some of the drain and source region dopants migrate a short distance under the gate dielectric. This means the actual distance between the source and drain regions, or effective gate length Leffective or Leff, is shorter than Lactual, the width of the gate material. It is the ratio of transistor width to Leff that determines drive strength. The amount by which Leff is shorter than Lactual and Ldrawn depends on the specific process and can vary significantly between manufacturers and between process generations. Although having a small Leff is important for high transistor drive it is also important to minimize the lateral diffusion, the difference between Lactual and Leff, to reduce parasitic capacitance that slows circuit operation and increase power consumption.
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