The FET Throws a Curve
In the first part of this article the field effect transistor (FET) was modeled as a simple on/off switch controlled by the voltage applied to their gate terminal for the purpose of explaining how basic CMOS logic circuits operated. The n-channel and p-channel FET (NFET and PFET) were shown to be complementary, i.e. active when the gate voltage applied was high and respectively and shut off otherwise. Unfortunately for logic designers, a real FET isn’t an ideal switch but rather a complex three dimensional physical construct whose full operational electrical properties, both intentional and parasitic, are rather complex when examined carefully. For example, circuit design engineers often use the Berkeley Short-channel IGFET (insulated gate FET) Model or BSIM. This partially physical, partially empirical computer model uses a large set of equations with 60 separate parameters to simulate FET operation .
Not to worry however, I will follow the wise advice given to Stephen Hawking when he wrote A Brief History of Time, stay away from mathematical formulas. Instead I will present real world FET operation graphically using families of curves that relate the current driven by the transistor as a function of the output voltage. Different curves are obtained by varying the voltage on the gate (control element). The data presented was obtained from BSIM model based simulations for a specific 0.13 um CMOS process currently available from a major semiconductor manufacturer.
Let’s consider two transistors, an NFET and a PFET. Both transistors have a width W of 1.0 micron and a drawn length L of 0.13 micron. The family of curves relating output current (I) versus output voltage (V) for the two transistors operating in an inverter type pull up/pull down configuration are shown in Figure 2. Notice that the NFET sinks the most current when it is pulling down from a high voltage (Vd = 1.0 V) with a high voltage on the gate. As the voltage on the gate is reduced the amount of current the NFET sinks at a given output voltage falls. The PFET sources the most current when it is pulling up from a low voltage (Vd = 0.0 V) with a low voltage on the gate. As the voltage on the gate is increased the amount of current the PFET sources at a given output voltage falls.
Also notice that the NFET can drive nearly three times as much current as a PFET of the same size. This is due to the fact that the mobility (ease of charge carrier movement for a given strength of applied electric field) of electrons is nearly three times higher than that of holes (remember back to part one of this article – the NFET transfers current in its channel region as electrons while the PFET transfers current as holes). The specific drive strength disparity between NFETs and PFETs has a central and significant influence on CMOS logic circuit design as we will see later.
Figure 2 Family of IV curves for 1.0 um NFET and PFET
The IV curves in Figure 2 are for nominally processed wafers. Manufacturing microscopic components like submicron long FETs is not an exact science and transistor characteristics will vary slightly from location to location on the same wafer, moderately from wafer to wafer in the same manufacturing batch (typically two dozen wafers or so), and more significantly, from batch to batch. This occurs due to variation in transistor dimensions, dopant concentrations, gate dielectric thickness and so on. To be successful, circuit designs implemented in integrated circuits must be tolerant of wide variations in transistor drive current, for example, from 30% below to 40% above the currents shown in Figure 2.
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