Circuit Design Basics – the Inverter
As discussed in the first part of this article, the fundamental CMOS logic gate is the basic inverter, which consists of an NFET and PFET arranged as pull down and pull up elements respectively and their gates tied together to the input node. The lengths of the transistors are assumed to be the minimum length permitted by the process, 0.13 um in our examples, as this provides maximum switching speed, smallest layout area, and minimum input capacitance and intrinsic power consumption. That leaves two variables – the width of the NFET and PFET, WN and WP respectively.
The performance of a logic gate that connects to no other circuit is a philosophical question similar to the old saw about whether a tree falling in the forest makes a sound if no one is around to hear it. That means in practice the output of a gate is connected to some degree of capacitive load. But the effect a given amount of capacitance has on a gate’s performance is directly tied to the size of the transistors of that gate. One method chip designers have come up with to express the performance of simple logic gates in a given technology in a size-independent way without ignoring the effect of output loading is the fan-out of four metric or FO4. The FO4
performance of a gate is its performance when its output is loaded by the input capacitance of four copies of the same gate. This scheme is useful because the larger and more powerful a simple CMOS gate is the proportionally higher its input capacitance is, so the FO4 performance is relatively constant for a given circuit topology regardless of size. This simple but useful loading scheme is shown in Figure 3.
Figure 3 Fan-out Four (FO4) Loading for Simple Gate Characterization.
Also shown in Figure 3 are the definitions of rising propagation delay Tpd[R] and falling propagation delay Tpd[F]. The description rising and falling with regards to a delay always references the change in the output signal because a given output edge may be caused by either a rising or falling transition on the active input depending on whether the gate is inverting or not. The delay times themselves are typically measured between the time the input waveform passes through 50% of the supply voltage and the time the output waveform passes through 50% of the supply voltage (remember that CMOS gates drive out a zero voltage level for a logic ‘0’ and a voltage equal to the power supply voltage for a logic ‘1’).
Output rise time and fall time (not shown) is quite different from rising delay and falling delay. Output rise time and fall time depends strictly on the shape of the output waveform without reference to an input transition. Rise time is typically specified as the time it takes for the output voltage to rise from 20% of the supply voltage to 80% of the supply voltage. Conversely fall time is typically specified as the time it takes the output voltage to fall from 80% of the supply voltage to 20% of the supply voltage. Rise and fall times are important to proper chip operation. Rise and fall times that are too slow cause excessive power consumption in gates with inputs connected to slow signals as well as causing inaccuracy in modeling gate timing. Rise and fall times that are too fast can cause disruptive levels of induced noise on signals that travel on wires adjacent to or above or below a wire with a fast signal.
As previously mentioned, for a given width an NFET can drive nearly three times as much current as a PFET. Common sense would dictate that for symmetrical switching performance (i.e balanced output rise time vs output fall time) that for a given size of NFET a PFET nearly three times wider should be used, that is WP/WN ~ 3. And indeed as can be seen in Figure 4, this is the case if switching symmetry is the only design criteria. Figure 4 shows the FO4 rise and fall time for an 0.13 um CMOS inverter with a total transistor width (WP+WN) of 10 um for varying ratios of WP/WN.
Figure 4. Inverter FO4 Rise and Fall Time as Function of WP/WN
The left side of the graph shows that for WP/WN ratio of 1.5 the output rise time of the inverter is 55 ps while the fall time is 40 ps (unless otherwise specified performance numbers given are for nominal transistor processing and room temperature operation with a 1.0 Volt supply). As the WP/WN ratio rises the rise time shrinks while the fall time grows as would be expected. The rise and fall time are balanced for WP/WN ~ 2.6. That is, an inverter with a 7.2 um wide PFET pull up transistor and a 2.8 um wide NFET pull down transistor.
However, in practice WP/WN ratios of 1.5 to 2.0 are often used for CMOS logic gates. One reason can be seen in Figure 5 which shows rising FO4 propagation delay (Tpd[R]), falling FO4 propagation delay (Tpd[F]), and average propagation delay (1/2*(Tpd[R]+Tpd[F])) for the same inverter circuit used for Figure 4.
Figure 5. Inverter FO4 Propagation Delay as Function of WP/WN
As would be expected the falling delay grows as the WP/WN ratio rises. The rising delay shrinks with rising WP/WN for a while as would be expected but then starts to grow again above about 2.3. The important observation to make is average propagation delay rises with increasing WP/WN. This is largely due to the fact that to increase WP/WN with a fixed total WP+WN, you must take away some amount of NFET width and replace it with the same amount of PFET width. Because NFETs have about three times the current drive per unit size as PFETs, such a trade-off lowers the total drive capability of the gate and increases average propagation delay.
Another reason that WP/WN ratio smaller than that need for symmetrical switching are often favored is for layout size and power considerations. In a given process a certain minimum transistor width must be specified for reliable device fabrication. Smaller WP/WN ratios allow smaller minimum layout area/minimum power gates for use in non-timing critical sections of logic. For example, if minimum transistor width is 0.4 um then the smallest 1.5 ratio inverter has WP + WN of 0.4 + 0.6 or 1.0 um while the smallest 2.5 ratio inverter has WP + WN of 1.4 um. The smaller inverter obviously takes up less area on the chip while perhaps less obviously consuming both lower dynamic and lower leakage power.
For the purposes of examining CMOS inverter performance as a function of operating conditions the WP/WN ratio is chosen to be 2.0. That means our circuit under consideration uses a 6.67 um wide PFET pull up transistor and a 3.33 um wide NFET pull down transistor. The two major external operating conditions that affect CMOS circuit performance are temperature and supply voltage. Computer hobbyists who overclock microprocessors know through empirical observation that the highest clock rate that a microprocessor can successfully operate at can be increased by increasing supply voltage (within absolute tolerance of the device of course), lowering the MPU’s operating temperature, or ideally, both.
This sensitivity of CMOS logic gate performance to operating conditions can be easily demonstrated and accurately quantified with circuit level simulation. The FO4 average propagation delay for our 6.67/3.33 inverter demonstration gate as a function of temperature and supply voltage can be seen as a three dimensional surface in the graph in Figure 6. Again this is for nominal transistor processing.
Figure 6. FO4 Average Propagation Delay vs Temperature, Supply Voltage.
The lowest average gate delay, less than 35 ps, is achieved at low temperature (0 deg C) and high supply voltage (1.1 Volt). The highest average gate delay, above 65 ps, is achieved at high temperature (120 deg C) and low supply voltage (0.7 V). It should be cautioned that many different circuit design styles are used inside a microprocessor (we will see some of them later on) and some of these respond to variation in operating conditions differently from static CMOS logic circuits whose typical characteristics are shown in Figure 6.
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