Logic of Computation
As was mentioned in the first part of this article, the inverter is useful for amplifying, buffering, and changing the logic sense of a signal but more complicated gates are need to build systems. The simplest and most common approach to building multi-input logic gates in CMOS is called static complementary logic. The general form of this type of gate is shown in Figure 7.
Figure 7. General CMOS Static Complementary Gate
This circuit is formed by tying the input signal to the supply voltage through a network of PFETs and to ground through a network of NFETs. Each of the inputs connects to the gate node of at least one PFET and one NFET. The PFET networks and NFET networks are complementary. That is, comparing the networks hierarchically, a series connection of 2 or more transistors whose gates are connected to a specific set of inputs in one network must be matched to a parallel arrangement of the same number of transistors whose gates are connected to the same set of inputs in the other network. This ensures that for all 2n possible combinations of n inputs the output is either connected to VDD through the PFET network or to VSS through the NFET network but never both. The hierarchical transistor network decomposition that results in a three input and-or-invert (AOI) gate is shown in Figure 8.
Figure 8. Derivation of a Static 3 input And-or-Invert (AOI) Gate
The sizing of transistors for maximum performance and switching symmetry is more complicated for multiple input CMOS gates than for the simple case of an inverter, because one or more paths between the output and VDD or VSS passes through multiple FETs connected in series. When the active signal flow is through series transistors the output drive is weakened. This is similar to how the effective resistance of resistors connected in series is the sum of the individual resistances. If n identical transistors are connected in series the signal drive strength through them is roughly 1/n of a single transistor. In general, drive symmetry is maintained by increasing the width of transistors used in a series signal path. This process is illustrated in Figure 9 with
three logic gates of approximately similar output drive strength and switching characteristics.
Figure 9. Transistor Sizing in Multiple Input Gates
The inverter is a simple CMOS inverter with a 4 um wide PFET and 2 um NFET. This is converted into a two input NAND gate by adding a PFET in parallel and NFET in series. The PFET size is unchanged but the NFET width is increased to 4 um because the two NFETs are connected in series. When the output of the two input NAND gate changes from a ‘1’ to a ‘0’ the drive strength of two 4 um wide NFETs is about the same as the single 2 um wide NFET in the simple inverter. Similarly, in a three input NAND gate the NFETs are sized at 6 um wide because there are three transistors in series.
Discuss (67 comments)