Conclusion and Summary
CMOS is an extraordinarily versatile technology. It allows logic functions to be implemented in a variety of ways, both static and dynamic. Static design approaches in CMOS provide robust logic functionality that consume no DC current other than transistor leakage when inputs are quiescent.
However equivalent sized n-channel and p-channel devices in CMOS have significantly different drive strength characteristics. This contributes to performance problems with some static logic circuit topologies suffering unduly from the parasitic capacitance of its own transistors.
For demanding applications like high performance microprocessors more sophisticated logic design methods based on dynamic circuit techniques can be applied. The advantages of dynamic logic approaches include potentially much higher performance than static logic allows as well as reduced input capacitance, layout area, and in some cases, reduced power consumption. The drawbacks of dynamic logic includes the addition of timing related requirements and constraints on inputs that complicates the logic and circuit design process as well as providing more opportunities for errors and bugs to creep in while increasing susceptibility to on-chip electrical noise. Also, dynamic circuits can undergo switching activity independently of input transitions, and this, along with the extra power needed to clock them, sometimes increases power consumption compared to a static implementation.
Nevertheless, without dynamic and clocked logic design techniques microprocessor clock rates today would arguably be less than half of what they are now. That is roughly the equivalent of two full semiconductor process generations of advancement. And that is why high end microprocessor design teams continue to pay the price in manpower, design complexity, power consumption, and increased time to market compared to the more widely taught and applied application specific integrated circuit (ASIC) design methodology that is based on combining the robust and forgiving nature of static CMOS logic with a highly automated, standard cell based design approach.
 Sheu, B., et al, “BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors”, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 4, August 1987, pp. 558-565.
 Chandrakasan, A., Bowhill, W., and Fox, F., “Design of High-Performance Microprocessor Circuits”, IEEE Press, 2001, ISBN 0-7803-6001-X, p. 129.
 Preston, R. et al, “Design of an 8-wide Superscalar RISC Microprocessor with Simultaneous Multithreading”, ISSCC 2002 Digest of Technical Papers, p. 334.
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