Making x86 Run Cool

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Power Consumption: Switching vs. Leakage

For microprocessors, and digital CMOS chips in general, power consumption is dominated by the current consumed to charge and discharge the parasitic capacitance associated with wires and transistors as 0 to 1 and 1 to 0 transitions race around the chip. This power, called dynamic or switching power, is represented by the formula P = C V2 F where P is power, C is the switching capacitance, V is the voltage swing (generally the supply voltage), and F is the switching frequency. Modern chips attempt to minimize dynamic power by reducing all three factors. The capacitance is minimized by clever logic design, clock gating, and intelligent floor planning to reduce the total length of interconnect. Besides the obvious approach of reducing the global power supply voltage, MPU designers sometimes minimize the switching voltage by the use of limited swing signaling (e.g. the operand buses in the Alpha EV6 integer units). Effective frequency minimization is accomplished by preventing signals from propagating down paths when and where they are not needed.

A second contributor to power consumption is leakage current. Each transistor in a CMOS chip leaks a tiny amount of current. Even with the tens of millions of transistors in modern MPUs the power consumption associated with leakage current is generally negligible compared to switching power. However, ultra low power MPUs are often put into idle or deep sleep states when not active. While dynamic power tracks reductions in clock frequency and switching activity, leakage current power remains relatively constant. The larger fraction of the time that a processor spends with its clock slowed or stopped, the more important the magnitude of leakage power becomes to the overall power consumption because the normally dominant C V2 F power term can be reduced arbitrarily all the way to zero by lowering F to zero. Leakage power is a function of the overall number and size of the transistors in a CMOS chip and increases exponentially with device temperature while generally varying linearly with supply voltage. Unlike switching power, there is generally little that chip designers can do to reduce leakage other than minimize the size and number of logic transistors in the design.

Unfortunately advances in modern semiconductor technology increases leakage current with each new generation process. This can be seen in Table 1, which shows extrapolated limitations to MOS transistor scaling [2]. History has always shown it is dangerous to predict limitations in semiconductor scaling, but out of six physical design parameters examined the fact that four of them are constrained by leakage considerations is significant.

<strong>Table 1 Practical Limits to Physical Scaling of MOS Transistors</strong>

Feature

Limit

Consideration

Dielectric Thickness

2.3 nm

Leakage (IGATE)

Junction Depth

30 nm

Resistance (RSDE)

Channel Doping

VT = 250 mV

Leakage (IOFF)

Source/Drain Extension under Diffusion

15 nm

Resistance (RINV)

Channel Length

0.06 um

Leakage (IOFF)

Gate Length

0.10 um

Leakage (IOFF)

As an illustration of the current state of the problem, Intel has disclosed that the 0.18 um, 6.5 million transistor, 17 mm2 XScale (second generation StrongARM) processor core consumes about 24 mW of power due to leakage current, or up to 5% of the full speed power consumption at 600 MHz at 1.3 Volts [3]. Leakage represents a much larger fraction of power when the device operates with 55 mW total power at 200 MHz and 0.7V. The leakage current power for 0.18 um x86 processors is undoubtedly much higher than 24 mW, possibly several hundred mW, because of their much greater die size, transistor count, and typically higher operating temperature.

Besides the incipient split between mobile and desktop/server x86 processor core designs, we will likely see semiconductor process differentiation between the different classes of MPUs in the future. While multiple Watts of leakage current power may be acceptable for 0.13 or 0.10 um desktop or server processor constantly consuming 50 or 100 Watts or more of switching power, much lower levels of leakage will be required for mobile processors targeting perhaps 10 Watts peak (thermal design) and under 1 Watt average switching power. Low power processes for the manufacture of mobile MPUs would have greater transistor effective gate length (Leff), gate dielectric thickness (tOX), and threshold voltages (VT) to reduce leakage. This would come at the cost of weaker transistors, increased logic propagation delay times, and reduced maximum operating frequency.


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