Making x86 Run Cool

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The forces of semiconductor process evolution and x86 market dynamics are forcing MPU products for the low power mobile markets to diverge from those intended for the higher power desktop and server markets. The increasing importance of leakage current power consumption in current and future CMOS processes means that mobile MPU designers cannot throw ever more logic transistors at chasing the tail of diminishing returns of IPC improvement (to paraphrase IBM research staff member Bob Montoye). Success lies instead in maximizing the performance of transistors that are already there. That is best accomplished by attempting to strike a balance between designing for high clock frequency and designing for high IPC.

The most important recent innovation in x86 MPU design is the trace cache. Although the trace cache was originally created to attack the frequency scalability problem of parallel x86 instruction decoders, it also offers an intriguing way to reduce the power consumption of mobile x86 MPUs. A side benefit of the trace cache is it allows high levels of parallelism in uop execution without requiring a concomitant degree of parallelism in the front-end x86 decoder.

A hypothetical 0.18 um low power x86 processor called Cool_x86 was described. It employs a number of performance enhancement and power reduction features including a trace cache, relatively short execution pipeline, improved branch prediction, and large L2 cache. The estimated power, performance, and computational energy efficiency characteristics of the Cool_x86 compare favorably to the recently introduced 1 GHz mobile Pentium III. It will be interesting to see how similar Cool_x86 is to the upcoming Intel ‘Banias’ core, an entirely new x86 core processor explicitly design for low power and mobile applications. The imminent arrival of the AMD ‘Palomino’ will also demonstrate what power reduction measures are possible in an evolutionary design heavily leveraged from an existing core.


[1] Krewell, K., ‘AMD Shoots Mustangs Doesn’t It?’, Microprocessor Report, Vol. 14, No. 11, November 2000, p. 11.

[2] Thompson, S., et al, ‘MOS Scaling: Transistor Challenges for the 21st Century’, Intel Technology Journal, Q3, 1998.

[3] Lawrence, T. et al., ‘A Scalable Performance 32b Microprocessor’, Digest of Technical Papers, ISSCC 2001, February 6, 2001, p. 230.

[4] D. Bhandarkar and J. Ding, ‘Performance Characterization of the Pentium Pro Processor’, Proceedings of the 3rd International Symposium on High Performance Computer Architecture, February 1997.

[5] Intel Corporation, ‘Mobile Intel Pentium III Processor in BGA2 and MicroPGA2 Packages’, Datasheet, Order # 249562-001, 2001.

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