[Note: The original version of this article made prominent mention of press reports from IDF that Intel planned to start pilot production of McKinley at the end of the year at 1.4 GHz. I have been informed that these reports were erroneous and no clock frequency target was disclosed. The article has been amended accordingly]
Better Late Than Never
If all goes as planned Intel will launch its first 64-bit processor within a few months. Developed under the code name ‘Merced’, the Itanium is the first of a line of processors implementing the controversial new instruction set architecture called IA-64. But in a curious turn of events, Intel has just demonstrated functional first silicon of Itanium’s reportedly potent successor, code named McKinley, at its recent developer’s forum even before the Itanium completes its extraordinarily drawn out pre-production phase and enters general commercial availability.
If Merced does indeed begin shipping for revenue in 2Q01 then it will be the final chapter in the story of a remarkably troubled microprocessor that stretches over a dozen years, as shown in Figure 1. In June 1994, Hewlett Packard and Intel announced that they were forming an alliance to jointly develop a new 64-bit architecture using existing Very Long Instruction Word (VLIW) technology as a starting point . At that point the 64-bit x86 processor Intel was developing under the code name P7 was quietly dropped in favor of the particular flavor of VLIW that HP researchers had been quietly working on for about five years.
Figure 1 Time Line for IA-64 Development
The IA-64 instruction set architecture that the two companies created is truly the product of design by committee  . A team of 6 Intel and 6 HP engineers met regularly to hash out the details of the architectural specification. In cases of a disagreement, the project leader, Intel’s John Crawford, was the ultimate arbiter. Along with an ISA specification, the team laid the groundwork for its first implementation in silicon. The code name for this device, Merced, was first revealed in late 1995 along with important details such as a planned introduction in 1998 and the 0.25 um device’s full x86 compatibility in hardware. However the Merced project suffered delays and schedule slips as the designers realized the full complexity of the machine they attempting to build was beyond both what they had planned for and what could be implemented in a single 0.25 um device. After rejecting such alternatives as radical simplification and multiple chip implementation, Intel bit the bullet and retargeted the Merced to its 0.18 um process, a decision which delayed it by about a year to 1999. Despite this setback Intel publicly predicted that Merced would ship in 1999 with ‘industry-leading performance’ as late as October 1997 .
Unfortunately for Intel and its IA-64 partners, the final physical design of the 0.18 um device did not progress well and the large team of engineers had great difficulty getting critical path timing to converge to meet the 800 MHz target clock rate. In the summer of 1998 Intel announced that Merced’s schedule would slip another eight months to deliveries in mid 2000. The official reason was that the verification effort was taking longer than expected. Unofficially, rumors had it that an extra stage was added to Merced’s execution pipeline to accommodate register file address generation and access, bringing the total to the current 10 stages for basic integer instructions. Progress was slow and tapeout didn’t occur until the summer of 1999. Intel obtained fast fab turn around and was able to demonstrate first silicon at its fall 1999 developers forum.
Since then Intel has been producing limited quantities of ‘Itaniums’ in what it calls a pilot production program. Intel claims to have shipped 50,000 processors in over 7000 systems to various computer manufacturers and software developers. Apparently most of these systems operate with processor clock rates well under the announced 800 MHz target clock rate, which has certainly done little to improve the reputation of Intel’s troubled 64-bit processor. This has even led some industry observers to suggest that Merced would never be competitive enough to serve as anything more than the role of IA-64 software development platform . What we do know is that the competition Merced/Itanium will face shipping in 2001 will be much more formidable than that it would have faced if it had shipped on time in 1998. Intel has long realized this and for the last year and a half has been rallying the IA-64 troops around the mantra ‘wait for McKinley!’.
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