Countdown to IA-64

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Intel’s excruciatingly long 64-bit MPU melodrama is finally approaching some degree of resolution. Merced/Itanium will likely be formally rolled out in a month or two while McKinley engineering samples and prototype systems continue to diffuse into the labs and offices of Intel’s IA-64 hardware and software development partners. Years of marketing hype, white papers, advocacy and criticism will give way to more tangible and objective measures of the success or failure of the IA-64 architecture. Expect a marketing campaign similar to the current Pentium 4 effort with an intense focus on individual applications that perform well, while ignoring those that are unflattering.

We probably already know the likely outcome based on the lessons of the last 15 years of competition between x86 and RISC processors – architecture is important but in terms of performance it is secondary to differences in implementation quality and process technology. Any advantage EPIC holds over RISC will likely be tenuous and scattered among narrow application niches. It will almost certainly be less than the gradually narrowing inherent advantages RISC still holds over x86 (See RISC vs. CICS Still Matters in this column). The sad fact for computer architects is that in the absence of flashes of genius or great fumbling, the first processor built using a next generation semiconductor process will likely be the fastest, coolest, and have the best price/performance ratio regardless of whether it is x86, RISC, or EPIC. From a metaphysical engineering point of view, Intel and HP claims of the technical superiority of EPIC over RISC are still quite dubious. But it is commercial success rather than abstract technical superiority that determines which architectures end up on or under desks and in server rooms.

The big picture might best be viewed by setting aside technical issues. Intel is entering the 64-bit MPU market with an architecture still enjoying an unparalleled breadth of industry support despite the schedule slips. Compaq, HP, IBM, and SGI all have their own line of proprietary 64-bit processors, yet have announced their intention to develop and sell systems using IA-64 processors (in fact replacing the HP and SGI architectures). Intel has the Xeon business model of success through standardization of server MPUs, chipsets, and even motherboards across multiple system vendors to achieve unmatched economies of scale. At the same time Intel is aggressively spending billions to bring multiple 0.13 um wafer fabs on line within the next few years. Unless IA-64 is a serious technical disaster of EPIC proportions (of which I can find no evidence or even plausible scenario) it seems assured of at least limited commercial success and a share of the expanding 64-bit MPU market. RISC vendors have to make aggressive and timely use of innovations like SMT, CMP, and huge off-chip bandwidth to counter Intel’s systematic cost advantages and ensure themselves a sufficiently large slice of the pie.


[1] Fuller, B. ‘Intel P7 petering out?’, Electronic Engineering Times, August 15, 1994, p. 1.

[2] Britt, R. ‘The Birth of a New Processor’, Electronic Business, January 2000, p. 62.

[3] Conversation with an HP member of IA-64 architecture committee, October 2000.

[4] Gwennap, L., ‘Merced Slips to Mid-2000’, Microprocessor Report, Vol. 12, No. 8, June 22, 1998, p. 1.

[5] Gwennap, L., ‘What’sWrong With Merced’, Microprocessor Report, Vol. 12, No. 10, August 3, 1998, p. 3.

[6] M. Schlansker, B. Rau, ‘EPIC: An Architecture for Instruction Level Parallel Processors’, HP Laboratories Report HPL-1999-111, February 2000.

[7] ‘IA-64 Application Developer’s Architecture Guide’, Intel Corporation, May 1999.

[8] Hwu, W., et al, ‘Compiler Technology for Future Microprocessors’, Proceedings of the IEEE, Vol. 83, No. 12, December 1995, p. 1625.

[9] Advance Program, 2001 IEEE International Solid-State Circuits Conference, p. 35.

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