We previously theorized that Intel’s TSX extensions in Haswell use the caches to provide transactional memory semantics. This article describes an alternative approach based on minimal changes to the CPU core, contrasts the advantages of the two techniques and discusses the expected implementation in Haswell.
Haswell Transactional Memory Alternatives
August 21, 2012 by
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ARM Goes 64-bit
August 14, 2012 by
The new ARMv8 architecture is classically British; a clean and elegant 64-bit instruction set, with compatibility for 32-bit software. The 64-bit mode eliminates many complicated and awkward features and will foster a larger and more diverse ARM ecosystem with new licensees and applications.
Computational Efficiency for CPUs and GPUs in 2012
July 25, 2012 by
New compute efficiency data shows GPUs with a clear edge over CPUs, but the gap is narrowing as CPUs adopt wide vectors (e.g. AVX). Surprisingly, a throughput CPU is the most energy efficient processor, offering hope for future architectures. Our data also shows some advantages of AMD’s Bulldozer, and the overhead associated with highly scalable server CPUs.
Sandy Bridge-EP Review
April 3, 2012 by
In our Sandy Bridge-EP and Romley platform review, we look at the performance and power efficiency gains for Intel’s latest server microprocessor on industry standard benchmarks including SPECcpu2006 and SPECpower_ssj2008. The results are impressive, Sandy Bridge-EP is clearly the best x86 server processor on the market, and Romley will be the platform of choice for the next 2 years.
Sandy Bridge-EP Launches
March 6, 2012 by
Sandy Bridge-EP is the first major overhaul for Intel servers since 2009, and nearly ever aspect has been enhanced. The processor pairs 8 cores with a large last level cache, DDR3 memory controller, QPI 1.1, integrated PCI-E and power management. This article provides an overview of the major features, including new I/O optimization and power capping techniques and discusses the expected impact.
Analysis of Haswell’s Transactional Memory
February 15, 2012 by
Intel’s upcoming Haswell microprocessors include transactional memory and hardware lock elision that are exposed through the Transactional Synchronization Extensions or TSX. In this article, I discuss TSX and predict the implementation details of Haswell’s transactional memory and expected adoption across the industry, based on my previous experience.
Medfield, Intel’s x86 Phone Chip
January 23, 2012 by
For 4 years, Intel has struggled to move into the market for mobile devices. Conventional wisdom holds that x86 is too inefficient for smart phones. The recently announced 32nm Medfield proves that x86 is a viable option and that Intel can design smart phone products. We explore the Medfield SoC and analyze the impact on Intel’s mobile strategy.
IBM z196 Mainframe Architecture
January 3, 2012 by
IBM’s mainframes are the oldest line of computers, dating back to 1964 and occupy a special place as the world’s first instruction set architecture. This longevity and extreme backwards compatibility are responsible for perhaps the most lucrative computer franchise. IBM’s z196 is the first mainframe with an out-of-order CMOS microprocessor, and also the first with an integrated L3 cache. These two innovations are largely responsible for a 30-40% improvement in performance over the previous generation z10.
ISSCC 2012 Preview
November 28, 2011 by
Highlights of the upcoming 2012 ISSCC include the first 22nm disclosures from Intel and several SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu on system level power for the K supercomputer.
Nvidia’s Kal-El Goes Asymmetric
October 5, 2011 by
Nvidia’s Kal-El sports a novel 5th ‘companion’ core to lower idle power. We look at the trade-offs and benefits to this approach and explain why it will be a strong tablet SoC, but only an incremental gain for smartphones.